diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 59377a5d8a28fd3aff7e3149e82f12fc2e85fbd9..302b0b85dce3b85c575cfec017a3f356eaa64cce 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -38,7 +38,8 @@
 -- [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
 --
 -- Usage:
--- > as 5, observe signals with radix decimal
+-- > as 5, observe signed signals with radix decimal, and observe unsigned
+--         signals with radix unsigend.
 -- > run -all
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -64,7 +65,9 @@ ARCHITECTURE tb OF tb_common_to_sreal IS
 
   SIGNAL a_real           : REAL := 0.0;
   SIGNAL a_sint           : INTEGER := 0;
-  SIGNAL a_slv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL a_uint           : NATURAL := 0;
+  SIGNAL a_slv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');  -- signed slv
+  SIGNAL a_ulv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');  -- unsigned slv
   SIGNAL dbg_resolution_w : INTEGER := 0;
   SIGNAL dbg_resolution   : REAL := 0.0;
 
@@ -103,10 +106,18 @@ BEGIN
         a_real <= v_real;
         a_sint <= TO_SINT(v_real, c_width, R);
         a_slv <= TO_SVEC(v_real, c_width, R);
+        IF I >= 0 THEN
+          a_uint <= TO_UINT(v_real, c_width, R);
+          a_ulv <= TO_UVEC(v_real, c_width, R);
+        END IF;
         WAIT UNTIL rising_edge(clk);
         -- Verify
         ASSERT a_sint = I REPORT "Wrong REAL to INTEGER conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR;
         ASSERT a_slv = v_slv REPORT "Wrong REAL to SLV conversion for I = " & INTEGER'IMAGE(I) SEVERITY ERROR;
+        IF I >= 0 THEN
+          ASSERT a_uint = I REPORT "Wrong REAL to NATURAL conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR;
+          ASSERT a_ulv = v_slv REPORT "Wrong REAL to unsigned SLV conversion for I = " & NATURAL'IMAGE(I) SEVERITY ERROR;
+        END IF;
       END LOOP;
       proc_wait_some_cycles(clk, 10);
     END LOOP;
@@ -123,30 +134,47 @@ BEGIN
     v_real := -7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real :=  6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real :=  6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real :=  7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real :=  7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real :=  6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real :=  6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real :=  7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real :=  7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     proc_wait_some_cycles(clk, 5);
 
     -- . Just overflow with 4 bit integers for -16.5 : +15.5
     v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real :=  15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real :=  15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     proc_wait_some_cycles(clk, 5);
 
+    -- . Negative clip to 0 for unsigned
+    v_real := -3.0; a_real <= v_real; a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    ASSERT         a_uint = 0 REPORT "Unexpected TO_UINT(< 0) : " & INTEGER'IMAGE(a_uint) & " /= 0" SEVERITY ERROR;
+    ASSERT TO_UINT(a_ulv) = 0 REPORT "Unexpected TO_UVEC(< 0) : " & INTEGER'IMAGE(TO_UINT(a_ulv)) & " /= 0" SEVERITY ERROR;
+
+    proc_wait_some_cycles(clk, 5);
     -- . Large overflow with 4 bit integers for << -16.5 : >> +15.5
+    v_real := -68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real := -58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real := -48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real := -38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+    v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real := -38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real := -48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real := -58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
-    v_real := -68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
     v_real :=  68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
+                                       a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); WAIT UNTIL rising_edge(clk);
 
     proc_wait_some_cycles(clk, 10);
     tb_end <= '1';
@@ -154,6 +182,10 @@ BEGIN
   END PROCESS;
 
   -- TO_SINT() and TO_SVEC() must always yield same result
-  ASSERT a_sint = TO_SINT(a_slv) REPORT "Unexpected difference between TO_SINT() and TO_SVEC() :" & INTEGER'IMAGE(a_sint) & " /= " & INTEGER'IMAGE(TO_SINT(a_slv));
+  ASSERT a_sint = TO_SINT(a_slv) REPORT "Unexpected difference between TO_SINT() and TO_SVEC() :" &
+                  INTEGER'IMAGE(a_sint) & " /= " & INTEGER'IMAGE(TO_SINT(a_slv)) SEVERITY ERROR;
 
+  -- TO_UINT() and TO_UVEC() must always yield same result
+  ASSERT a_uint = TO_UINT(a_ulv) REPORT "Unexpected difference between TO_UINT() and TO_UVEC() :" &
+                  INTEGER'IMAGE(a_uint) & " /= " & INTEGER'IMAGE(TO_SINT(a_ulv)) SEVERITY ERROR;
 END tb;