-Increased witdh of gap setting (and others) to 24 bits as 16 bits is not

 enough to create the duty cycle needed for ARTS (9375/160000).
-During init state, the block gen does not start until XON is high. This fixes
 the internal data flushing when en=1 but xon=0.

libraries/base/diag/src/vhdl/diag_block_gen.vhd

@@ -125,8 +125,10 @@ begin
           v.bsn_cnt     := ctrl.bsn_init;
           v.mem_cnt     := v_mem_low_adrs; 
           if r.blk_en = '1' then       -- Wait until enabled
-            v.rd_ena      := '1';
-            v.state       := s_block;        
+            if out_siso.xon='1' then   -- Wait until XON is 1
+              v.rd_ena      := '1';
+              v.state       := s_block;
+            end if;
           end if;
           
         when s_block =>

libraries/base/diag/src/vhdl/diag_pkg.vhd

@@ -102,10 +102,10 @@ PACKAGE diag_pkg IS
   CONSTANT c_diag_bg_reg_adr_w   : NATURAL := ceil_log2(c_diag_bg_reg_nof_dat);
   
   CONSTANT c_diag_bg_mode_w               : NATURAL :=  8;
-  CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 16;   
+  CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 24;   
   CONSTANT c_diag_bg_blocks_per_sync_w    : NATURAL := 24;   
-  CONSTANT c_diag_bg_gapsize_w            : NATURAL := 16;
-  CONSTANT c_diag_bg_mem_adrs_w           : NATURAL := 16;  
+  CONSTANT c_diag_bg_gapsize_w            : NATURAL := 24;
+  CONSTANT c_diag_bg_mem_adrs_w           : NATURAL := 24;  
   CONSTANT c_diag_bg_mem_low_adrs_w       : NATURAL := c_diag_bg_mem_adrs_w;  
   CONSTANT c_diag_bg_mem_high_adrs_w      : NATURAL := c_diag_bg_mem_adrs_w;
   CONSTANT c_diag_bg_bsn_init_w           : NATURAL := 64;