libraries/base/diag/src/vhdl/diag_pkg.vhd · f3df7090fe1176aa3198806bd9b96a8d9c1758cc · RTSD / HDL

7 years ago

-Increased witdh of gap setting (and others) to 24 bits as 16 bits is not · f3df7090

Daniel van der Schuur authored 7 years ago

 enough to create the duty cycle needed for ARTS (9375/160000).
-During init state, the block gen does not start until XON is high. This fixes
 the internal data flushing when en=1 but xon=0.

f3df7090

History

-Increased witdh of gap setting (and others) to 24 bits as 16 bits is not

Daniel van der Schuur authored 7 years ago

 enough to create the duty cycle needed for ARTS (9375/160000).
-During init state, the block gen does not start until XON is high. This fixes
 the internal data flushing when en=1 but xon=0.

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