diff --git a/libraries/technology/base/technology_pkg.vhd b/libraries/technology/base/technology_pkg.vhd
index 72882b491cf82ebe4020e4253c9fab0065a3593a..d99395239c9dc93b7f963199d32f119a5abd8953 100644
--- a/libraries/technology/base/technology_pkg.vhd
+++ b/libraries/technology/base/technology_pkg.vhd
@@ -27,10 +27,12 @@ PACKAGE technology_pkg IS
 
   -- Technology identifiers
   CONSTANT c_tech_inferred           : INTEGER := 0;
-  CONSTANT c_tech_stratixiv          : INTEGER := 1;
-  CONSTANT c_tech_arria10            : INTEGER := 2;
-  CONSTANT c_tech_stratix10          : INTEGER := 3;
-  CONSTANT c_tech_nof_technologies   : INTEGER := 4;
+  CONSTANT c_tech_virtex4            : INTEGER := 1;   -- e.g. used on RSP3 for Lofar
+  CONSTANT c_tech_stratixiv          : INTEGER := 2;   -- e.g. used on UniBoard1
+  CONSTANT c_tech_virtex6            : INTEGER := 3;   -- e.g. used on Roach2 for Casper
+  CONSTANT c_tech_virtex7            : INTEGER := 4;   -- e.g. used on Roach3 for Casper
+  CONSTANT c_tech_arria10            : INTEGER := 5;   -- e.g. used on UniBoard2
+  CONSTANT c_tech_nof_technologies   : INTEGER := 6;
 
   -- Functions
   FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 4697ebd3aed24cdee8de9a94fdec28c700d23864..377b1604883504148997ae10f77419a64b72bcb3 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
 hdl_lib_name = tech_memory
 hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses = technology ip_altera_mf
+hdl_lib_uses = technology ip_altera_mf ip_xilinx_core
 
 build_sim_dir = $HDL_BUILD_DIR
 build_synth_dir = 
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 3b469fdc2cfe4600c802d6ed8be2d3ee767db125..184de5f57fd3c05c2b16cd42ffbcdef620bd6efe 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
   GENERIC (
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 08a19f2ccf1013c1a270558798c556ba0e574c8c..786ab45cc2f3153e775f6657a194c1246f1c8245 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
   GENERIC (
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 64b00d13a48f6b4e24fbc7cb8eb0211bef1f51f5..ce3e4919b959333b36d9bbc3128c44fab1012b23 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
   GENERIC (
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 3e0680269212d15a9aaa950a0be7ffc57b40a111..162e9f7caed59a144d359ef2b34ecbddca32fcc0 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_ram_r_w IS
   GENERIC (
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 83774a3ebde3f095efb913cb9f097e479fd7936c..4702c46f546f6f013728382fdc845d37ec1c59f6 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_altera_mf_lib;
+LIBRARY ip_xilinx_core_lib;
 
 ENTITY tech_memory_rom_r IS
   GENERIC (
diff --git a/libraries/technology/xilinx/xilinx_core/hdllib.cfg b/libraries/technology/xilinx/xilinx_core/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..375f8631e4803be2785b1ec2c0ba10a28a885d9f
--- /dev/null
+++ b/libraries/technology/xilinx/xilinx_core/hdllib.cfg
@@ -0,0 +1,10 @@
+hdl_lib_name = ip_xilinx_core
+hdl_library_clause_name = ip_xilinx_core_lib
+hdl_lib_uses = 
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+        
+test_bench_files =