From f1742a7a5f9714bd87b0b45f3fb8fe4ec795ddd7 Mon Sep 17 00:00:00 2001 From: Erik Kooistra <kooistra@astron.nl> Date: Wed, 28 May 2014 05:44:44 +0000 Subject: [PATCH] Added empty library ip_xilinx_core_lib in technology/xilinx/xilinx_core, to show that the multi technology support works in tech_memory_*.vhd. --- libraries/technology/base/technology_pkg.vhd | 10 ++++++---- libraries/technology/memory/hdllib.cfg | 2 +- libraries/technology/memory/tech_memory_ram_cr_cw.vhd | 1 + .../technology/memory/tech_memory_ram_crw_crw.vhd | 1 + .../technology/memory/tech_memory_ram_crwk_crw.vhd | 1 + libraries/technology/memory/tech_memory_ram_r_w.vhd | 1 + libraries/technology/memory/tech_memory_rom_r.vhd | 1 + libraries/technology/xilinx/xilinx_core/hdllib.cfg | 10 ++++++++++ 8 files changed, 22 insertions(+), 5 deletions(-) create mode 100644 libraries/technology/xilinx/xilinx_core/hdllib.cfg diff --git a/libraries/technology/base/technology_pkg.vhd b/libraries/technology/base/technology_pkg.vhd index 72882b491c..d99395239c 100644 --- a/libraries/technology/base/technology_pkg.vhd +++ b/libraries/technology/base/technology_pkg.vhd @@ -27,10 +27,12 @@ PACKAGE technology_pkg IS -- Technology identifiers CONSTANT c_tech_inferred : INTEGER := 0; - CONSTANT c_tech_stratixiv : INTEGER := 1; - CONSTANT c_tech_arria10 : INTEGER := 2; - CONSTANT c_tech_stratix10 : INTEGER := 3; - CONSTANT c_tech_nof_technologies : INTEGER := 4; + CONSTANT c_tech_virtex4 : INTEGER := 1; -- e.g. used on RSP3 for Lofar + CONSTANT c_tech_stratixiv : INTEGER := 2; -- e.g. used on UniBoard1 + CONSTANT c_tech_virtex6 : INTEGER := 3; -- e.g. used on Roach2 for Casper + CONSTANT c_tech_virtex7 : INTEGER := 4; -- e.g. used on Roach3 for Casper + CONSTANT c_tech_arria10 : INTEGER := 5; -- e.g. used on UniBoard2 + CONSTANT c_tech_nof_technologies : INTEGER := 6; -- Functions FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING; diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg index 4697ebd3ae..377b160488 100644 --- a/libraries/technology/memory/hdllib.cfg +++ b/libraries/technology/memory/hdllib.cfg @@ -1,6 +1,6 @@ hdl_lib_name = tech_memory hdl_library_clause_name = tech_memory_lib -hdl_lib_uses = technology ip_altera_mf +hdl_lib_uses = technology ip_altera_mf ip_xilinx_core build_sim_dir = $HDL_BUILD_DIR build_synth_dir = diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd index 3b469fdc2c..184de5f57f 100644 --- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd +++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd @@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. LIBRARY ip_altera_mf_lib; +LIBRARY ip_xilinx_core_lib; ENTITY tech_memory_ram_cr_cw IS GENERIC ( diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd index 08a19f2ccf..786ab45cc2 100644 --- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd +++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd @@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. LIBRARY ip_altera_mf_lib; +LIBRARY ip_xilinx_core_lib; ENTITY tech_memory_ram_crw_crw IS GENERIC ( diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd index 64b00d13a4..ce3e4919b9 100644 --- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd +++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd @@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. LIBRARY ip_altera_mf_lib; +LIBRARY ip_xilinx_core_lib; ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges GENERIC ( diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd index 3e06802692..162e9f7cae 100644 --- a/libraries/technology/memory/tech_memory_ram_r_w.vhd +++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd @@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. LIBRARY ip_altera_mf_lib; +LIBRARY ip_xilinx_core_lib; ENTITY tech_memory_ram_r_w IS GENERIC ( diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd index 83774a3ebd..4702c46f54 100644 --- a/libraries/technology/memory/tech_memory_rom_r.vhd +++ b/libraries/technology/memory/tech_memory_rom_r.vhd @@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. LIBRARY ip_altera_mf_lib; +LIBRARY ip_xilinx_core_lib; ENTITY tech_memory_rom_r IS GENERIC ( diff --git a/libraries/technology/xilinx/xilinx_core/hdllib.cfg b/libraries/technology/xilinx/xilinx_core/hdllib.cfg new file mode 100644 index 0000000000..375f8631e4 --- /dev/null +++ b/libraries/technology/xilinx/xilinx_core/hdllib.cfg @@ -0,0 +1,10 @@ +hdl_lib_name = ip_xilinx_core +hdl_library_clause_name = ip_xilinx_core_lib +hdl_lib_uses = + +build_sim_dir = $HDL_BUILD_DIR +build_synth_dir = + +synth_files = + +test_bench_files = -- GitLab