Skip to content
Snippets Groups Projects
Commit f15afa5d authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

processed review comments

parent 998c37e4
Branches
No related tags found
1 merge request!392added qsfp_leds_v2 and connected the DDR cal OK signal.
Pipeline #76355 passed
...@@ -439,11 +439,11 @@ architecture str of unb2c_test is ...@@ -439,11 +439,11 @@ architecture str of unb2c_test is
signal ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi; signal ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
signal ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso; signal ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- DDR calibration_ok signals are set to '1' by default such that the corresponding -- DDR calibration_ok signals are set to '0' by default such that the corresponding
-- LED is turned ON when no IP is instantiated. This is prefered over turning it off -- LED is turned OFF when no IP is instantiated. This is prefered over turning it on
-- as that would indicate a (false) calibration error. -- as that would indicate a (false) correct calibration.
signal ddr_I_cal_ok : std_logic := '1'; signal ddr_I_cal_ok : std_logic := '0';
signal ddr_II_cal_ok : std_logic := '1'; signal ddr_II_cal_ok : std_logic := '0';
-- UDP streaming ports for 1GbE I and 1GbE II -- UDP streaming ports for 1GbE I and 1GbE II
-- . eth_0 = 1GbE I -- . eth_0 = 1GbE I
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment