From f15afa5d369c7e213085cd996f63762358d5c414 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Wed, 20 Mar 2024 10:32:27 +0100 Subject: [PATCH] processed review comments --- .../designs/unb2c_test/src/vhdl/unb2c_test.vhd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd index 712628d7f5..e03a41f2c7 100644 --- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd +++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd @@ -439,11 +439,11 @@ architecture str of unb2c_test is signal ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi; signal ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso; - -- DDR calibration_ok signals are set to '1' by default such that the corresponding - -- LED is turned ON when no IP is instantiated. This is prefered over turning it off - -- as that would indicate a (false) calibration error. - signal ddr_I_cal_ok : std_logic := '1'; - signal ddr_II_cal_ok : std_logic := '1'; + -- DDR calibration_ok signals are set to '0' by default such that the corresponding + -- LED is turned OFF when no IP is instantiated. This is prefered over turning it on + -- as that would indicate a (false) correct calibration. + signal ddr_I_cal_ok : std_logic := '0'; + signal ddr_II_cal_ok : std_logic := '0'; -- UDP streaming ports for 1GbE I and 1GbE II -- . eth_0 = 1GbE I -- GitLab