Reinier van der Walle
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
  signal ram_diag_data_buf_ddr_MB_II_mosi  : t_mem_mosi;
  signal ram_diag_data_buf_ddr_MB_II_miso  : t_mem_miso;

+  -- DDR calibration_ok signals are set to '1' by default such that the corresponding
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
-      g_pulse_us      => 1000 / (10**9 / c_mm_clk_freq)  -- nof clk cycles to get us period
+      g_mm_pulse_us   => 1000 / (10**9 / c_mm_clk_freq), 
+      g_dp_pulse_us   => 1000 / (10**9 / c_dp_clk_freq)
    )
    port map (
-      rst             => mm_rst,
-      clk             => mm_clk,
-      green_led_arr   => qsfp_green_led_arr,
-      red_led_arr     => qsfp_red_led_arr
+      mm_rst             => mm_rst,
+      mm_clk             => mm_clk,
+      dp_rst             => dp_rst,
+      dp_clk             => dp_clk,
+      dp_pps             => dp_pps,
+      ddr_I_cal_ok       => ddr_I_cal_ok,
+      ddr_II_cal_ok      => ddr_II_cal_ok,