- Added pipelines for sosi_ctrl signal recovery.

- Changed settings for requantizer by adding c_wpfb_out_dat_significant_w

applications/apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_processing.vhd

@@ -139,8 +139,9 @@ ARCHITECTURE str OF apertif_unb1_correlator_processing IS
   CONSTANT c_wpfb_nof_points            : NATURAL := 64;                   -- = 1024, N point FFT
   CONSTANT c_wpfb_nof_taps              : NATURAL := 8;                    -- = 8 nof taps n the filter
   CONSTANT c_wpfb_coef_w                : NATURAL := 16;                   --FIXME: 9b does not work; needs updated coefficient files.
-  CONSTANT c_wpfb_in_dat_w          : NATURAL := 8;                    --FIXME: should be 6b at some point
+  CONSTANT c_wpfb_in_dat_w              : NATURAL := 6;                    --FIXME: In simulation there are 6bit values used in the BG.
   CONSTANT c_wpfb_out_dat_w             : NATURAL := 16;                   --FIXME: Could be wider but is currently 9b to avoid the need for quantization: 9b -> mult -> 18b -> accu -> 32b at the corr output.
+  CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(c_wpfb_in_dat_w = 6, 10, 12);
   CONSTANT c_wpfb_use_separate          : BOOLEAN := FALSE;                -- = false for complex input, true for two real inputs
   CONSTANT c_wpfb_use_reorder           : BOOLEAN := FALSE;
 
@@ -188,7 +189,10 @@ ARCHITECTURE str OF apertif_unb1_correlator_processing IS
   SIGNAL reinterleave_in_arr                         : t_dp_sosi_arr(c_nof_cor_inputs-1 DOWNTO 0);
   SIGNAL reinterleave_out_arr                        : t_dp_sosi_arr(c_nof_interleaved_streams-1 DOWNTO 0);
   
+  SIGNAL dp_pipeline_src_out                         : t_dp_sosi;
+
   -- Filterbank and Correlator
+  SIGNAL wpfb_eop                                    : STD_LOGIC;  
   SIGNAL wpfb_snk_in_ctrl                            : t_dp_sosi;                    
   SIGNAL wpfb_snk_in_arr                             : t_dp_sosi_arr(c_nof_interleaved_streams-1 DOWNTO 0);
   SIGNAL wpfb_src_out_arr                            : t_dp_sosi_arr(c_nof_interleaved_streams-1 DOWNTO 0);
@@ -312,7 +316,7 @@ BEGIN
       g_deint_block_size  => 1,
       g_nof_out           => 1,
       g_inter_block_size  => 1,
-      g_use_ctrl          => FALSE,
+      g_use_ctrl          => TRUE,
       g_dat_w             => g_usr_data_w,
       g_use_complex       => c_use_complex,
       g_align_out         => TRUE
@@ -324,15 +328,53 @@ BEGIN
       src_out_arr => reinterleave_out_arr(I DOWNTO I)
     );
   END GENERATE;
+  ---------------------------------------------------------------------------------------------
+  -- FIXME: It would be nice if the control signals from the output of the dp_reinterleave unit 
+  --        were OK. They are now not OK and therefor some trickery has to be done to generate
+  --        proper sosi-control signals for the wpfb. 
+  --------------------------------------------------------------------------------------------
   
-  p_add_st_ctrl : PROCESS(reinterleave_out_arr)
+  -----------------------------------------------------------------------------
+  -- DP Pipeline to recover the sosi-control signals after the reinterleaving 
+  -----------------------------------------------------------------------------
+  u_st_ctrl_pipe : ENTITY dp_lib.dp_pipeline
+  GENERIC MAP(
+    g_pipeline  => 1  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+
+    snk_in       => reinterleave_in_arr(0),
+    src_out      => dp_pipeline_src_out
+  );
+
+  -- EOP should be one later then the other signals due to reinterleavinga
+  u_pipe_eop : ENTITY common_lib.common_pipeline
+  GENERIC MAP (
+    g_pipeline  => 2, 
+    g_in_dat_w  => 1,
+    g_out_dat_w => 1
+  )
+  PORT MAP (
+    rst         => dp_rst,
+    clk         => dp_clk,
+    in_dat      => slv(reinterleave_in_arr(0).eop),
+    sl(out_dat) => wpfb_eop
+  );
+
+  -----------------------------------------------------------------------------
+  -- Merge reinterleaved data again with pipelined sosi-control signals. 
+  -----------------------------------------------------------------------------
+  p_add_st_ctrl : PROCESS(reinterleave_out_arr, dp_pipeline_src_out)
   BEGIN
     FOR I IN 0 TO c_nof_interleaved_streams-1 LOOP                  
-      wpfb_snk_in_arr(I) <= reinterleave_out_arr(I);
---      wpfb_snk_in_arr(i)      <= dp_pipeline_src_out; -- SOSI ctrl
---      wpfb_snk_in_arr(i).data <= reinterleave_out_arr(i).data;
---      wpfb_snk_in_arr(i).im   <= reinterleave_out_arr(i).im;
---      wpfb_snk_in_arr(i).re   <= reinterleave_out_arr(i).re;
+      wpfb_snk_in_arr(i)       <= dp_pipeline_src_out; -- SOSI ctrl
+      wpfb_snk_in_arr(i).data  <= reinterleave_out_arr(i).data;
+      wpfb_snk_in_arr(i).im    <= reinterleave_out_arr(i).im;
+      wpfb_snk_in_arr(i).re    <= reinterleave_out_arr(i).re;
+      wpfb_snk_in_arr(i).eop   <= wpfb_eop;
+      wpfb_snk_in_arr(i).valid <= reinterleave_out_arr(i).valid;
     END LOOP;
   END PROCESS;
   
@@ -410,7 +452,7 @@ BEGIN
     GENERIC MAP (
       g_complex             => TRUE,
       g_representation      => "SIGNED",      
-      g_lsb_w               => c_wpfb_out_dat_w-c_cor_in_dat_w,               
+      g_lsb_w               => c_wpfb_out_dat_significant_w-c_cor_in_dat_w,               
       g_lsb_round           => FALSE,           
       g_lsb_round_clip      => FALSE,      
       g_msb_clip            => FALSE,