Initial commit

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/apertif_unb1_correlator_lite.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+-- Purpose:
+
+ENTITY apertif_unb1_correlator_lite IS
+  GENERIC (
+    g_design_name             : STRING  := "apertif_unb1_correlator_lite";
+    g_design_note             : STRING  := "correlator without terminals"; 
+    g_sim                     : BOOLEAN := FALSE; -- Overridden by TB
+    g_sim_level               : NATURAL := 0; 
+    g_sim_fast                : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
+    g_sim_unb_nr              : NATURAL := 0;
+    g_sim_node_nr             : NATURAL := 0;
+    g_stamp_date              : NATURAL := 0;    -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time              : NATURAL := 0;    -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn               : NATURAL := 0     -- SVN revision    -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK           : IN    STD_LOGIC; -- System Clock
+    PPS           : IN    STD_LOGIC; -- System Sync
+    WDI           : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA          : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB          : INOUT STD_LOGIC; -- FPGA interconnect line
+                  
+    -- Others     
+    VERSION       : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID            : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO        : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+    
+    -- I2C Interface to Sensors
+    sens_sc       : INOUT STD_LOGIC;
+    sens_sd       : INOUT STD_LOGIC;
+  
+    -- 1GbE Control Interface
+    ETH_clk       : IN    STD_LOGIC;
+    ETH_SGIN      : IN    STD_LOGIC;
+    ETH_SGOUT     : OUT   STD_LOGIC;
+
+    -- Transceiver clocks
+    SA_CLK        : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+    SB_CLK        : IN  STD_LOGIC; -- SerDes clock FN-BN (tr_mesh)
+
+    -- Mesh Serial I/O
+    FN_BN_0_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_0_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_1_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_1_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_2_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_2_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_3_TX    : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_3_RX    : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+    -- Serial I/O: 10GbE receivers 
+    SI_FN_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_0_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_1_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_2_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+    SI_FN_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+    SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+    SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+    SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+    SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+    SI_FN_RSTN    : OUT   STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+                                           -- So we need to assign a '1' to it.
+  );
+END apertif_unb1_correlator_lite;
+
+
+ARCHITECTURE str OF apertif_unb1_correlator_lite IS
+  
+BEGIN
+
+  u_revision : ENTITY work.apertif_unb1_correlator_nodes
+  GENERIC MAP (    
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,        
+    g_sim_level   => g_sim_level,
+    g_sim_fast    => g_sim_fast,               
+    g_sim_unb_nr  => g_sim_unb_nr, 
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date, 
+    g_stamp_time  => g_stamp_time, 
+    g_stamp_svn   => g_stamp_svn
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK           => CLK,           
+    PPS           => PPS,           
+    WDI           => WDI,           
+    INTA          => INTA,          
+    INTB          => INTB,          
+                                   
+    VERSION       => VERSION,       
+    ID            => ID,            
+    TESTIO        => TESTIO,
+                                   
+    sens_sc       => sens_sc,       
+    sens_sd       => sens_sd,       
+                                   
+    ETH_clk       => ETH_clk,       
+    ETH_SGIN      => ETH_SGIN,      
+    ETH_SGOUT     => ETH_SGOUT,     
+                                   
+    SA_CLK        => SA_CLK,        
+    SB_CLK        => SB_CLK,        
+                                   
+    FN_BN_0_TX    => FN_BN_0_TX,    
+    FN_BN_0_RX    => FN_BN_0_RX,    
+    FN_BN_1_TX    => FN_BN_1_TX,    
+    FN_BN_1_RX    => FN_BN_1_RX,    
+    FN_BN_2_TX    => FN_BN_2_TX,    
+    FN_BN_2_RX    => FN_BN_2_RX,    
+    FN_BN_3_TX    => FN_BN_3_TX,    
+    FN_BN_3_RX    => FN_BN_3_RX,    
+                                   
+    SI_FN_0_TX    => SI_FN_0_TX,    
+    SI_FN_0_RX    => SI_FN_0_RX,    
+    SI_FN_1_TX    => SI_FN_1_TX,    
+    SI_FN_1_RX    => SI_FN_1_RX,    
+    SI_FN_2_TX    => SI_FN_2_TX,    
+    SI_FN_2_RX    => SI_FN_2_RX,    
+    SI_FN_3_TX    => SI_FN_3_TX,    
+    SI_FN_3_RX    => SI_FN_3_RX,    
+                                   
+    SI_FN_0_CNTRL => SI_FN_0_CNTRL, 
+    SI_FN_1_CNTRL => SI_FN_1_CNTRL, 
+    SI_FN_2_CNTRL => SI_FN_2_CNTRL, 
+    SI_FN_3_CNTRL => SI_FN_3_CNTRL, 
+    SI_FN_RSTN    => SI_FN_RSTN    
+  );
+END str;
+

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg

+hdl_lib_name = apertif_unb1_correlator_lite
+hdl_library_clause_name = apertif_unb1_correlator_lite_lib
+hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus/qsys_apertif_unb1_correlator.qsys .
+    ../../src/hex/ hex
+    $UNB/Firmware/dsp/filter/build/data/ mif
+
+modelsim_copy_files = 
+    ../../src/hex hex
+    $UNB/Firmware/dsp/filter/build/data/ mif
+
+synth_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_lite/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
+    ../../src/vhdl/apertif_unb1_correlator_pkg.vhd
+    ../../src/vhdl/mmm_apertif_unb1_correlator.vhd
+    ../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_input.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_mesh.vhd
+    ../../src/vhdl/node_apertif_unb1_correlator_processing.vhd
+    ../../src/vhdl/apertif_unb1_correlator_nodes.vhd
+    apertif_unb1_correlator_lite.vhd
+    
+test_bench_files = 
+    tb_apertif_unb1_correlator_lite.vhd
+
+quartus_qsf_files = 
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    ../../quartus/apertif_unb1_correlator_pins.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_lite/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.qip
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc    

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/tb_apertif_unb1_correlator_lite.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Description:
+-- Usage:
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_apertif_unb1_correlator_lite IS
+END tb_apertif_unb1_correlator_lite;
+
+ARCHITECTURE tb OF tb_apertif_unb1_correlator_lite IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 7; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
+
+  CONSTANT c_cable_delay     : TIME := 12 ns;
+  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
+  CONSTANT c_sa_clk_period   : TIME := 6.4 ns;  
+  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_pps_period      : NATURAL := 1000; 
+
+
+  -- DUT
+  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+  SIGNAL sa_clk              : STD_LOGIC := '1';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC;
+  SIGNAL eth_rxp             : STD_LOGIC;
+  
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+ 
+  SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_1_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_2_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+  SIGNAL fn_bn_3_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
+  
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+  
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_dut : ENTITY work.apertif_unb1_correlator_lite
+    GENERIC MAP (
+      g_sim         => c_sim,
+      g_sim_unb_nr  => c_unb_nr,
+      g_sim_node_nr => c_node_nr
+    )
+    PORT MAP (
+      -- GENERAL
+      CLK         => clk,
+      PPS         => pps,
+      WDI         => WDI,
+      INTA        => INTA,
+      INTB        => INTB,
+
+      sens_sc     => sens_scl,
+      sens_sd     => sens_sda,
+
+      -- Others
+      VERSION     => VERSION,
+      ID          => ID,
+      TESTIO      => TESTIO,
+
+      -- 1GbE Control Interface
+      ETH_clk     => eth_clk,
+      ETH_SGIN    => eth_rxp,
+      ETH_SGOUT   => eth_txp,
+      
+      -- Transceiver clocks
+      SA_CLK      => sa_clk,  --  : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+      SB_CLK      => sa_clk,
+
+      -- Serial I/O
+      SI_FN_0_RX  => si_fn_0_tx,
+      SI_FN_1_RX  => si_fn_0_tx,
+      SI_FN_2_RX  => si_fn_0_tx,
+      SI_FN_3_RX  => si_fn_0_tx,
+
+      FN_BN_0_RX  => fn_bn_0_tx,
+      FN_BN_0_TX  => fn_bn_0_tx,
+
+      FN_BN_1_RX  => fn_bn_1_tx,
+      FN_BN_1_tX  => fn_bn_1_tx,
+
+      FN_BN_2_RX  => fn_bn_2_tx,
+      FN_BN_2_TX  => fn_bn_2_tx,
+
+      FN_BN_3_RX  => fn_bn_3_tx, 
+      FN_BN_3_TX  => fn_bn_3_tx  
+    );
+
+END tb;