Merge branch 'master' into L2SDP-942

libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd

@@ -31,6 +31,8 @@
 --   . The read latency is not adapted. Ensure that the Controller and Peripheral use the same 
 --     read-latency.
 --   . Both AXI4-lite and MM use ready latency = 0 for waitrequest/ready.
+--   . AXI4-lite is assumed to use byte addressed registers while MM uses word addressed 
+--     registers.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd

@@ -109,9 +109,9 @@ PACKAGE BODY axi4_lite_pkg IS
     VARIABLE v_mm_copi : t_mem_copi := c_mem_copi_rst;
   BEGIN
     IF axi4_copi.awvalid = '1' THEN
-      v_mm_copi.address := axi4_copi.awaddr;
+      v_mm_copi.address := "00" & axi4_copi.awaddr(c_axi4_lite_address_w-1 DOWNTO 2); -- convert byte addressed to word addressed.
     ELSE
-      v_mm_copi.address := axi4_copi.araddr;
+      v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w-1 DOWNTO 2); -- convert byte addressed to word addressed.
     END IF;
     v_mm_copi.wrdata(c_axi4_lite_data_w-1 DOWNTO 0) := axi4_copi.wdata;
     v_mm_copi.wr                                    := axi4_copi.awvalid;
@@ -131,14 +131,14 @@ PACKAGE BODY axi4_lite_pkg IS
   FUNCTION func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) RETURN t_axi4_lite_copi IS
     VARIABLE v_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
   BEGIN
-    v_axi4_copi.awaddr  := mm_copi.address;  
+    v_axi4_copi.awaddr  := mm_copi.address(c_axi4_lite_address_w-3 DOWNTO 0) & "00"; -- convert word addressed to byte addressed.
     v_axi4_copi.awprot  := (OTHERS => '0');  
     v_axi4_copi.awvalid := mm_copi.wr;  
     v_axi4_copi.wdata   := mm_copi.wrdata(c_axi4_lite_data_w-1 DOWNTO 0);  
     v_axi4_copi.wstrb   := (OTHERS => '1'); -- Either ignored or all bytes selected.  
     v_axi4_copi.wvalid  := mm_copi.wr;  
     v_axi4_copi.bready  := '1'; -- Unsupported by MM, assuming always ready.  
-    v_axi4_copi.araddr  := mm_copi.address;  
+    v_axi4_copi.araddr  := mm_copi.address(c_axi4_lite_address_w-3 DOWNTO 0) & "00"; -- convert word addressed to byte addressed.  
     v_axi4_copi.arprot  := (OTHERS => '0');  
     v_axi4_copi.arvalid := mm_copi.rd;  
     v_axi4_copi.rready  := '1'; -- Unsupported by MM, assuming always ready.  

libraries/io/eth/hdllib.cfg

 hdl_lib_name = eth
 hdl_library_clause_name = eth_lib
-hdl_lib_uses_synth = dp common diag tech_tse
+hdl_lib_uses_synth = dp common diag tech_tse axi4
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 
@@ -28,6 +28,7 @@ synth_files =
     src/vhdl/eth_tester_tx.vhd
     src/vhdl/eth_tester_rx.vhd
     src/vhdl/eth_tester.vhd
+    src/vhdl/eth_tester_axi4_wrapper.vhd
 
 test_bench_files = 
     src/vhdl/eth_statistics.vhd

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
     ip_arria10_e1sg_fifo   ip_arria10_e1sg_fifo_lib
     ip_arria10_e2sg_fifo   ip_arria10_e2sg_fifo_lib
+    ip_ultrascale_fifo     ip_arria10_ultrascale_lib
 
 synth_files =
     tech_fifo_component_pkg.vhd

libraries/technology/fifo/tech_fifo_component_pkg.vhd

@@ -352,5 +352,67 @@ PACKAGE tech_fifo_component_pkg IS
   );
   END COMPONENT;
    
+  -----------------------------------------------------------------------------
+  -- ip_ultrascale
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_ultrascale_fifo_sc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC ;
+    clock   : IN STD_LOGIC ;
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    empty   : OUT STD_LOGIC ;
+    full    : OUT STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+  COMPONENT ip_ultrascale_fifo_dc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT ip_ultrascale_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL := 20;
+    g_rddat_w   : NATURAL := 10
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
   
 END tech_fifo_component_pkg;

libraries/technology/fifo/tech_fifo_dc.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_dc IS
   GENERIC (
@@ -89,4 +90,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
 
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_dc
+    GENERIC MAP (g_dat_w, g_nof_words)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_dc_mixed_widths IS
   GENERIC (
@@ -89,4 +90,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
  
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_dc_mixed_widths
+    GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_sc.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_sc IS
   GENERIC (
@@ -87,4 +88,10 @@ BEGIN
     PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
   END GENERATE;
   
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_sc
+    GENERIC MAP (g_dat_w, g_nof_words)
+    PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/ip_ultrascale/fifo/hdllib.cfg

+hdl_lib_name = ip_ultrascale_fifo
+hdl_library_clause_name = ip_ultrascale_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_ultrascale
+
+synth_files =
+    ip_ultrascale_fifo_sc.vhd
+    ip_ultrascale_fifo_dc.vhd
+    ip_ultrascale_fifo_dc_mixed_widths.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_dc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_dc;
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_dc IS
+
+BEGIN
+   -- xpm_fifo_async: Asynchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_async_inst : xpm_fifo_async
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      CDC_SYNC_STAGES => 3,       -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words),   -- DECIMAL
+      READ_DATA_WIDTH => g_dat_w,  -- DECIMAL
+      READ_MODE => "std",          -- String
+      RELATED_CLOCKS => 0,         -- DECIMAL
+      SIM_ASSERT_CHK => 0,         -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404",  -- String
+      WAKEUP_TIME => 0,            -- DECIMAL
+      WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+   )
+   port map (
+      almost_empty => OPEN,        -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,     -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,       -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,             -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => rdempty,               -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => wrfull,                 -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => rdusedw,       -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => wrusedw,       -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_clk => rdclk,                -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+                                      -- free running clock.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                     -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => wrclk,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL := 20;
+    g_rddat_w   : NATURAL := 10
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_dc_mixed_widths;
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_dc_mixed_widths IS
+    
+BEGIN
+   -- xpm_fifo_async: Asynchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_async_inst : xpm_fifo_async
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      CDC_SYNC_STAGES => 3,       -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),   -- DECIMAL
+      READ_DATA_WIDTH => g_rddat_w,      -- DECIMAL
+      READ_MODE => "std",         -- String
+      RELATED_CLOCKS => 0,        -- DECIMAL
+      SIM_ASSERT_CHK => 0,        -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404", -- String
+      WAKEUP_TIME => 0,           -- DECIMAL
+      WRITE_DATA_WIDTH => g_wrdat_w,     -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+   )
+   port map (
+      almost_empty => OPEN,        -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,     -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,       -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,             -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => rdempty,               -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => wrfull,                 -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => rdusedw,       -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => wrusedw,       -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_clk => rdclk,                -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+                                      -- free running clock.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                     -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => wrclk,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+
+END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_sc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC ;
+    clock   : IN STD_LOGIC ;
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    empty   : OUT STD_LOGIC ;
+    full    : OUT STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_sc;
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_sc IS
+
+BEGIN
+   -- xpm_fifo_sync: Synchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_sync_inst : xpm_fifo_sync
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words),   -- DECIMAL
+      READ_DATA_WIDTH => g_dat_w,  -- DECIMAL
+      READ_MODE => "std",         -- String
+      SIM_ASSERT_CHK => 0,        -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404",  -- String
+      WAKEUP_TIME => 0,           -- DECIMAL
+      WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+
+   )
+   port map (
+      almost_empty => OPEN,           -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,            -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,             -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,                -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => empty,                 -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => full,                   -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => OPEN,          -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => usedw,         -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                    -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => clock,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+
+END SYN;

libraries/technology/ip_ultrascale/ram/hdllib.cfg

+hdl_lib_name = ip_ultrascale_ram
+hdl_library_clause_name = ip_ultrascale_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_ultrascale
+
+synth_files =
+#    ip_ultrascale_true_dual_port_ram_dual_clock.vhd
+#    ip_ultrascale_simple_dual_port_ram_dual_clock.vhd
+#    ip_ultrascale_simple_dual_port_ram_single_clock.vhd
+    
+#    ip_ultrascale_ram_crwk_crw.vhd
+    ip_ultrascale_ram_crw_crw.vhd
+    ip_ultrascale_ram_cr_cw.vhd
+#    ip_ultrascale_ram_r_w.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate RAM IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_ram_cr_cw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "none"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclk     : IN  STD_LOGIC ;
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclk     : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END ip_ultrascale_ram_cr_cw;
+
+
+ARCHITECTURE SYN OF ip_ultrascale_ram_cr_cw IS
+
+BEGIN
+
+  ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+  
+  ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
+
+   -- xpm_memory_sdpram: Simple Dual Port RAM
+   -- Xilinx Parameterized Macro, version 2022.1
+   xpm_memory_sdpram_inst : xpm_memory_sdpram
+   generic map (
+      ADDR_WIDTH_A => g_adr_w,              -- DECIMAL
+      ADDR_WIDTH_B => g_adr_w,              -- DECIMAL
+      AUTO_SLEEP_TIME => 0,                 -- DECIMAL
+      BYTE_WRITE_WIDTH_A => 32,             -- DECIMAL
+      CASCADE_HEIGHT => 0,                  -- DECIMAL
+      CLOCKING_MODE => "independent_clock", -- String
+      ECC_MODE => "no_ecc",                 -- String
+      MEMORY_INIT_FILE => g_init_file,      -- String
+      MEMORY_INIT_PARAM => "0",             -- String
+      MEMORY_OPTIMIZATION => "true",        -- String
+      MEMORY_PRIMITIVE => "auto",           -- String
+      MEMORY_SIZE => g_nof_words,           -- DECIMAL
+      MESSAGE_CONTROL => 0,                 -- DECIMAL
+      READ_DATA_WIDTH_B => g_dat_w,         -- DECIMAL
+      READ_LATENCY_B => g_rd_latency,       -- DECIMAL
+      READ_RESET_VALUE_B => "0",            -- String
+      RST_MODE_A => "SYNC",                 -- String
+      RST_MODE_B => "SYNC",                 -- String
+      SIM_ASSERT_CHK => 0,                  -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_EMBEDDED_CONSTRAINT => 0,         -- DECIMAL
+      USE_MEM_INIT => 1,                    -- DECIMAL
+      USE_MEM_INIT_MMI => 0,                -- DECIMAL
+      WAKEUP_TIME => "disable_sleep",       -- String
+      WRITE_DATA_WIDTH_A => g_dat_w,        -- DECIMAL
+      WRITE_MODE_B => "no_change",          -- String
+      WRITE_PROTECT => 1                    -- DECIMAL
+   )
+   port map (
+
+      dbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      doutb => q,                       -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+
+      sbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port B.
+
+      addra => wraddress,               -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
+      addrb => rdaddress,               -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
+      clka => wrclk,                    -- 1-bit input: Clock signal for port A. Also clocks port B when
+                                        -- parameter CLOCKING_MODE is "common_clock".
+
+      clkb => rdclk,                    -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
+                                        -- "common_clock".
+
+      dina => data,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+
+      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+                                              
+      injectdbiterra => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterra => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      regceb => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      rstb => '0',                      -- 1-bit input: Reset signal for the final port B output register
+                                        -- stage. Synchronously resets output port doutb to the value specified
+                                        -- by parameter READ_RESET_VALUE_B.
+
+      sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
+
+      wea(0) => wren                    -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+                                        -- for port A input data port dina. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dina to address addra. For example, to
+                                        -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
+                                        -- is 32, wea would be 4'b0010.
+
+   );
+
+   -- End of xpm_memory_sdpram_inst instantiation
+
+
+END SYN;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate RAM IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+  
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_ram_crw_crw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "none"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clk_a     : IN STD_LOGIC  := '1';
+    clk_b     : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END ip_ultrascale_ram_crw_crw;
+
+
+ARCHITECTURE SYN OF ip_ultrascale_ram_crw_crw IS
+  
+BEGIN
+
+  ASSERT g_rd_latency=1 OR g_rd_latency=2  REPORT "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+  ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
+  
+   -- xpm_memory_tdpram: True Dual Port RAM
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_memory_tdpram_inst : xpm_memory_tdpram
+   generic map (
+      ADDR_WIDTH_A => g_adr_w,               -- DECIMAL
+      ADDR_WIDTH_B => g_adr_w,               -- DECIMAL
+      AUTO_SLEEP_TIME => 0,            -- DECIMAL
+      BYTE_WRITE_WIDTH_A => g_dat_w,        -- DECIMAL
+      BYTE_WRITE_WIDTH_B => g_dat_w,        -- DECIMAL
+      CASCADE_HEIGHT => 0,             -- DECIMAL
+      CLOCKING_MODE => "independent_clock", -- String
+      ECC_MODE => "no_ecc",            -- String
+      MEMORY_INIT_FILE => g_init_file,      -- String
+      MEMORY_INIT_PARAM => "0",        -- String
+      MEMORY_OPTIMIZATION => "true",   -- String
+      MEMORY_PRIMITIVE => "block",      -- String
+      MEMORY_SIZE => g_nof_words,             -- DECIMAL
+      MESSAGE_CONTROL => 0,            -- DECIMAL
+      READ_DATA_WIDTH_A => g_dat_w,         -- DECIMAL
+      READ_DATA_WIDTH_B => g_dat_w,         -- DECIMAL
+      READ_LATENCY_A => g_rd_latency,   -- DECIMAL
+      READ_LATENCY_B => g_rd_latency,   -- DECIMAL
+      READ_RESET_VALUE_A => "0",       -- String
+      READ_RESET_VALUE_B => "0",       -- String
+      RST_MODE_A => "SYNC",            -- String
+      RST_MODE_B => "SYNC",            -- String
+      SIM_ASSERT_CHK => 0,             -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_EMBEDDED_CONSTRAINT => 0,    -- DECIMAL
+      USE_MEM_INIT => 1,               -- DECIMAL
+      USE_MEM_INIT_MMI => 0,           -- DECIMAL
+      WAKEUP_TIME => "disable_sleep",  -- String
+      WRITE_DATA_WIDTH_A => g_dat_w,   -- DECIMAL
+      WRITE_DATA_WIDTH_B => g_dat_w,   -- DECIMAL
+      WRITE_MODE_A => "no_change",     -- String
+      WRITE_MODE_B => "no_change",     -- String
+      WRITE_PROTECT => 1               -- DECIMAL
+   )
+   port map (
+      dbiterra => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      dbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      douta => q_a,                     -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+      doutb => q_b,                     -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+      sbiterra => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port A.
+
+      sbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port B.
+
+      addra => address_a,               -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
+      addrb => address_b,               -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
+      clka => clk_a,                    -- 1-bit input: Clock signal for port A. Also clocks port B when
+                                        -- parameter CLOCKING_MODE is "common_clock".
+
+      clkb => clk_b,                    -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
+                                        -- "common_clock".
+
+      dina => data_a,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+      dinb => data_b,                     -- WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
+      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+
+      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+                                              
+      injectdbiterra => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectdbiterrb => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterra => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterrb => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      regcea => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      regceb => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      rsta => '0',                      -- 1-bit input: Reset signal for the final port A output register
+                                        -- stage. Synchronously resets output port douta to the value specified
+                                        -- by parameter READ_RESET_VALUE_A.
+
+      rstb => '0',                      -- 1-bit input: Reset signal for the final port B output register
+                                        -- stage. Synchronously resets output port doutb to the value specified
+                                        -- by parameter READ_RESET_VALUE_B.
+
+      sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
+      wea(0) => wren_a,                       -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+                                        -- for port A input data port dina. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dina to address addra. For example, to
+                                        -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
+                                        -- is 32, wea would be 4'b0010.
+
+      web(0) => wren_a                        -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
+                                        -- for port B input data port dinb. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dinb to address addrb. For example, to
+                                        -- synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
+                                        -- is 32, web would be 4'b0010.
+
+   );
+
+   -- End of xpm_memory_tdpram_inst instantiation
+				
+END SYN;

libraries/technology/memory/hdllib.cfg

 hdl_lib_name = tech_memory
 hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
     ip_arria10_e1sg_ram   ip_arria10_e1sg_ram_lib
     ip_arria10_e2sg_ram   ip_arria10_e2sg_ram_lib
+    ip_ultrascale_ram     ip_ultrascale_ram_lib
 
 synth_files =
     tech_memory_component_pkg.vhd

libraries/technology/memory/tech_memory_component_pkg.vhd

@@ -516,4 +516,52 @@ PACKAGE tech_memory_component_pkg IS
   );
   END COMPONENT;
 
+  -----------------------------------------------------------------------------
+  -- ip_ultrascale
+  -----------------------------------------------------------------------------
+  COMPONENT ip_ultrascale_ram_crw_crw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "none"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clk_a     : IN STD_LOGIC  := '1';
+    clk_b     : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+    
+  COMPONENT ip_ultrascale_ram_cr_cw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "none"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclk     : IN  STD_LOGIC ;
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclk     : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
 END tech_memory_component_pkg;

libraries/technology/memory/tech_memory_ram_cr_cw.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_ram_lib;
 LIBRARY ip_arria10_e3sge3_ram_lib;
 LIBRARY ip_arria10_e1sg_ram_lib;
 LIBRARY ip_arria10_e2sg_ram_lib;
+LIBRARY ip_ultrascale_ram_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
   GENERIC (
@@ -88,4 +89,10 @@ BEGIN
     PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
   END GENERATE;
  
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_ram_cr_cw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+  END GENERATE; 
+
 END ARCHITECTURE;

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_ram_lib;
 LIBRARY ip_arria10_e3sge3_ram_lib;
 LIBRARY ip_arria10_e1sg_ram_lib;
 LIBRARY ip_arria10_e2sg_ram_lib;
+LIBRARY ip_ultrascale_ram_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
   GENERIC (
@@ -95,4 +96,11 @@ BEGIN
     PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   END GENERATE;
 
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_ram_crw_crw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+
+ 
 END ARCHITECTURE;