Skip to content
Snippets Groups Projects
Commit e9c44d8c authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

added yaml entries for unb2c_test design

parent 8a0bf9f5
Branches
No related tags found
1 merge request!161Resolve L2SDP-514
Hide whitespace changes
Inline Side-by-side
boards/uniboard2c/designs/unb2c_test/unb2c_test.fpga.yaml 0 → 100644
+ 266
− 0
View file @ e9c44d8c
schema_name : args
schema_version: 1.0
schema_type : fpga
hdl_library_name: unb2c_test
fpga_name : unb2c_test
fpga_description: "FPGA design unb2c_test"
parameters:
- { name: c_nof_streams_1GbE_UDP, value: 2 }
- { name: c_def_1GbE_block_size, value: 20 }
- { name: c_nof_streams_10GbE_UDP, value: 72 }
- { name: c_def_10GbE_block_size, value: 900 }
- { name: c_nof_streams_qsfp, value: 24 }
- { name: c_nof_streams_ring, value: 24 }
- { name: c_nof_streams_back0, value: 24 }
- { name: c_ddr_db_buf_nof_data, value: 1024 }
- { name: c_nof_streams_jesd204b, value: 12 }
- { name: c_jesd_db_buf_nof_data, value: 131072 }
peripherals:
# ctrl_unb2c_board
- peripheral_name: unb2c_board/system_info
lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- peripheral_name: unb2c_board/wdi
mm_port_names:
- REG_WDI
- peripheral_name: unb2c_board/unb2_fpga_sens
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
- peripheral_name: unb2c_board/ram_scrap
mm_port_names:
- RAM_SCRAP
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
# Heater
- peripheral_name: util/heater
mm_port_names:
- REG_HEATER
# 1GbE
- peripheral_name: diag/diag_block_gen
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- { name: g_buf_dat_w, value: 32 }
- { name: g_buf_addr_w, value: ceil_log2(c_def_1GbE_block_size) }
mm_port_names:
- REG_DIAG_BG_1GBE
- RAM_DIAG_BG_1GBE
- peripheral_name: diag/diag_tx_seq
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_1GBE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_BSN_MONITOR_1GBE
- peripheral_name: diag/diag_data_buffer
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_def_1GbE_block_size }
mm_port_names:
- REG_DIAG_DATA_BUFFER_1GBE
- RAM_DIAG_DATA_BUFFER_1GBE
- peripheral_name: diag/diag_rx_seq
peripheral_group: eth_1gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_1GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_1GBE
# 10GbE
- peripheral_name: diag/diag_block_gen
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
- { name: g_buf_dat_w, value: 64 }
- { name: g_buf_addr_w, value: ceil_log2(c_def_10GbE_block_size) }
mm_port_names:
- REG_DIAG_BG_10GBE
- RAM_DIAG_BG_10GBE
- peripheral_name: diag/diag_tx_seq
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_10GBE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_BSN_MONITOR_10GBE
- peripheral_name: diag/diag_data_buffer
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
- { name: g_data_w, value: 64 }
- { name: g_nof_data, value: c_def_10GbE_block_size }
mm_port_names:
- REG_DIAG_DATA_BUFFER_10GBE
- RAM_DIAG_DATA_BUFFER_10GBE
- peripheral_name: diag/diag_rx_seq
peripheral_group: eth_10gbe
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_10GbE_UDP }
mm_port_names:
- REG_DIAG_TX_SEQ_10GBE
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
peripheral_group: qsfp_ring
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
mm_port_names:
- REG_TR_10GBE_QSFP_RING
- peripheral_name: tr_10GbE/tr_10GbE_eth10g
peripheral_group: qsfp_ring
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_qsfp + c_nof_streams_ring }
mm_port_names:
- REG_ETH10G_QSFP_RING
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy
peripheral_group: back0
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_back0 }
mm_port_names:
- REG_TR_10GBE_BACK0
- peripheral_name: tr_10GbE/tr_10GbE_eth10g
peripheral_group: back0
parameter_overrides:
- { name: g_nof_macs, value: c_nof_streams_back0 }
mm_port_names:
- REG_ETH10G_BACK0
# DDR4 : MB I
- peripheral_name: ddr/io_ddr
peripheral_group: MB_I
mm_port_names:
- REG_IO_DDR_MB_I
- peripheral_name: diag/diag_tx_seq
peripheral_group: MB_I
mm_port_names:
- REG_DIAG_TX_SEQ_DDR_MB_I
- peripheral_name: diag/diag_rx_seq
peripheral_group: MB_I
mm_port_names:
- REG_DIAG_RX_SEQ_DDR_MB_I
- peripheral_name: diag/diag_data_buffer
peripheral_group: ddr_MB_I
parameter_overrides:
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_ddr_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_DDR_MB_I
- RAM_DIAG_DATA_BUFFER_DDR_MB_I
# DDR4 : MB II
- peripheral_name: ddr/io_ddr
peripheral_group: MB_II
mm_port_names:
- REG_IO_DDR_MB_II
- peripheral_name: diag/diag_tx_seq
peripheral_group: MB_II
mm_port_names:
- REG_DIAG_TX_SEQ_DDR_MB_II
- peripheral_name: diag/diag_rx_seq
peripheral_group: MB_II
mm_port_names:
- REG_DIAG_RX_SEQ_DDR_MB_II
- peripheral_name: diag/diag_data_buffer
peripheral_group: ddr_MB_II
parameter_overrides:
- { name: g_data_w, value: 32 }
- { name: g_nof_data, value: c_ddr_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_DDR_MB_II
- RAM_DIAG_DATA_BUFFER_DDR_MB_II
# JESD
- peripheral_name: tech_jesd204b/jesd_ctrl
mm_port_names:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
mm_port_names:
- JESD204B
- peripheral_name: dp/dp_bsn_source
mm_port_names:
- REG_BSN_SOURCE
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
mm_port_names:
- REG_BSN_MONITOR_INPUT
- peripheral_name: diag/diag_data_buffer
peripheral_group: bsn
parameter_overrides:
- { name: g_nof_streams, value: c_nof_streams_jesd204b }
- { name: g_data_w, value: 16 }
- { name: g_nof_data, value: c_jesd_db_buf_nof_data }
mm_port_names:
- REG_DIAG_DATA_BUFFER_BSN
- RAM_DIAG_DATA_BUFFER_BSN
libraries/base/diag/diag.peripheral.yaml
+ 114
− 2
View file @ e9c44d8c
......@@ -97,5 +97,117 @@ peripherals:
field_description: ""
number_of_fields: g_nof_data
address_offset: 0x0
mm_width: g_data_w
user_width: g_data_w
- peripheral_name: diag_block_gen # pi_diag_block_gen.py
peripheral_description: "Block generator (BG)"
parameters:
# Parameters of mms_diag_block_gen.vhd
- { name: g_nof_streams, value: 1 }
- { name: g_buf_dat_w, value: 16 }
- { name: g_buf_addr_w, value: 7 }
mm_ports:
# MM port for mms_diag_block_gen.vhd
- mm_port_name: REG_DIAG_BG
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "Block gen control."
number_of_mm_ports: 1
fields:
- - field_name: enable
address_offset: 0x0
bit_offset: 0
mm_width: 1
- - field_name: enable_sync
address_offset: 0x0
bit_offset: 1
mm_width: 1
- - field_name: samples_per_packet
address_offset: 0x4
- - field_name: blocks_per_sync
address_offset: 0x8
- - field_name: gapsize
address_offset: 0xc
- - field_name: mem_low_adrs
address_offset: 0x10
- - field_name: mem_high_adrs
address_offset: 0x14
- - field_name: bsn_init
address_offset: 0x18
user_width: 64
radix: uint64
# MM port for mms_diag_block_gen.vhd
- mm_port_name: RAM_DIAG_BG
mm_port_type: RAM
mm_port_span: ceil_pow2( 2**g_buf_addr_w * ceil_div(g_buf_dat_w, c_word_w)) * MM_BUS_SIZE
mm_port_description: "Block gen buffer memory, contains the data patterns to be generated."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: ""
number_of_fields: 2**g_buf_addr_w
address_offset: 0x0
user_width: g_buf_dat_w
- peripheral_name: diag_tx_seq # pi_diag_tx_seq.py
peripheral_description: "TX test sequence"
parameters:
# Parameters of mms_diag_tx_seq.vhd
- { name: g_nof_streams, value: 1 }
- { name: g_mm_broadcast, value: False }
mm_ports:
# MM port for mms_diag_tx_seq.vhd
- mm_port_name: REG_DIAG_TX_SEQ
mm_port_type: REG
mm_port_span: 4 * MM_BUS_SIZE
mm_port_description: "TX test sequence control."
number_of_mm_ports: sel_a_b(g_mm_broadcast, 1, g_nof_streams)
fields:
- - field_name: control
address_offset: 0x0
mm_width: 3
- - field_name: init
address_offset: 0x4
- - field_name: tx_cnt
address_offset: 0x8
access_mode: RO
- - field_name: modulo
address_offset: 0xc
- peripheral_name: diag_rx_seq # pi_diag_rx_seq.py
peripheral_description: "RX test sequence"
parameters:
# Parameters of mms_diag_rx_seq.vhd
- { name: g_nof_streams, value: 1 }
mm_ports:
# MM port for mms_diag_rx_seq.vhd
- mm_port_name: REG_DIAG_RX_SEQ
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "RX test sequence control."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: control
address_offset: 0x0
mm_width: 2
- - field_name: result
address_offset: 0x4
access_mode: RO
mm_width: 2
- - field_name: rx_cnt
address_offset: 0x8
access_mode: RO
- - field_name: rx_sample
address_offset: 0xc
access_mode: RO
- - field_name: step_0
address_offset: 0x10
- - field_name: step_1
address_offset: 0x14
- - field_name: step_2
address_offset: 0x18
- - field_name: step_3
address_offset: 0x1c
libraries/base/util/util.peripheral.yaml 0 → 100644
+ 23
− 0
View file @ e9c44d8c
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: util
hdl_library_description: "Util Heater."
peripherals:
- peripheral_name: heater # pi_heater.py
peripheral_description: "Heater component, see util_heater.vhd"
mm_ports:
# MM port for util_heater.vhd
- mm_port_name: REG_HEATER
mm_port_type: REG
mm_port_span: 32 * MM_BUS_SIZE
mm_port_description: "Heater control."
fields:
- - field_name: enable
field_description: "Enable"
number_of_fields: 25
address_offset: 0x0
libraries/io/ddr/ddr.peripheral.yaml 0 → 100644
+ 41
− 0
View file @ e9c44d8c
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: ddr
hdl_library_description: "Double data rate memory"
peripherals:
- peripheral_name: io_ddr # pi_io_ddr.py
peripheral_description: "DDR controller"
mm_ports:
# MM port for io_ddr_reg.vhd
- mm_port_name: REG_IO_DDR
mm_port_type: REG
mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: "DDR controller registers."
number_of_mm_ports: 1
fields:
- - field_name: burstbegin
address_offset: 0x0
access_mode: WO
mm_width: 1
- - field_name: wr_not_rd
address_offset: 0x4
access_mode: WO
mm_width: 1
- - field_name: done
address_offset: 0x8
access_mode: RO
mm_width: 1
- - field_name: address
address_offset: 0x14
access_mode: WO
- - field_name: burstsize
address_offset: 0x18
access_mode: WO
- - field_name: flush
address_offset: 0x1c
mm_width: 1
libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml 0 → 100644
+ 179
− 0
View file @ e9c44d8c
schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: tr_10GbE
hdl_library_description: "Network peripherals for 10GbE."
peripherals:
- peripheral_name: tr_10GbE_unb2legacy # pi_nw_10GbE_unb2legacy.py / pi_tr_10GbE.py / pi_tr_10GbE_unb2.py
peripheral_description: |
"M&C of Intel Low Latency (LL) 10GbE MAC control status register (CSR) see [1]
The LL 10GbE MAC is used with the legacy address map option of the old 10GbE MAC, see [2], this implies:
. Some registers have a different address offset in [1] and [2]
. The 36 bit registers are stored at word 0 = [31:0] and word 1 = [3:0] = [35:32] in [1], but in [2]
they are stored with their 4 most significant bits first and their 32 least significant bits last, so
with word 0 = [3:0] = [35:32] and word 1 = [31:0].
Here the address map and 36 bit word order from [2] are used.
[1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf
[2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf
"
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
mm_ports:
# MM port for reg_mac_mosi = mac_mosi in ip_arria10_e1sg_eth_10g.vhd
# Use tr_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses
- mm_port_name: REG_TR_10GBE_MAC
mm_port_type: REG
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
- - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
- - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
- - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
- - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
- - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
- - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
- - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
- - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
- - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
- - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
- - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
- - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
- - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
- - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
- - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
- - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
- - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
- - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
- - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
- - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
- - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
- - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
- - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
- - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
- - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
- - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
- - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
- - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
- - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
- - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
- - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
- - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
- - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
- - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
- - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
- - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
- - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
- - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
- - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
- - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
- - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
- - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
- - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
- - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
- - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
- - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
- - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
- - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
- - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
- - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
- - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
- - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
- - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
- - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
- - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
- - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
- - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
- - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
- - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
- - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
- - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
- - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: tr_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
peripheral_description: "10GbE link status register"
parameters:
# Parameters of nw_10GbE.vhd / tr_10GbE.vhd
- { name: g_nof_macs, value: 1 }
mm_ports:
# MM port for reg_eth10g_mosi in ip_arria10_e1sg_eth_10g.vhd / common_reg_r_w_dc.vhd
- mm_port_name: REG_TR_10GBE_ETH10G
mm_port_type: REG
mm_port_description: ""
number_of_mm_ports: g_nof_macs
fields:
- - field_name: tx_snk_out_xon
field_description: ""
address_offset: 0x0
mm_width: 1
bit_offset: 0
access_mode: RO
- - field_name: xgmii_tx_ready
field_description: ""
address_offset: 0x0
mm_width: 1
bit_offset: 1
access_mode: RO
- - field_name: xgmii_link_status
field_description: ""
address_offset: 0x0
mm_width: 2
bit_offset: 2
access_mode: RO
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment