Merge branch 'L2SDP-502' into 'master'

Use v.busy, instead of r.busy, to allow start_pulse at mm_done, to support...

Closes L2SDP-502

See merge request desp/hdl!159

doc/erko_hdl_design_article.txt

@@ -111,10 +111,16 @@ Implementation steps:
     SIGNAL r             : t_reg;
     SIGNAL nxt_r         : t_reg;
 
-  . -- Memoryless signals in p_comb (wires used as local auxiliary variables)
-    SIGNAL s             : t_comb;
+  . -- Memoryless signals and auxiliary variables in p_comb
+    -- . For unique representation of variables in p_comb as signal wires, the p_comb
+    --   should assign each field in t_comb only once to a variable. It is allowed to
+    --   reasign a t_comb variable in p_comb, so use it as a temporary auxiliary
+    --   variable, but then only the last assignment value will be visible via the
+    --   signal dbg_wires in the Wave window.
+    SIGNAL dbg_wires     : t_comb;
 
-  . -- Structural signals (wires used to connect components and IO)
+  . -- Structural signals (wires used to connect r, nxt_r to other components and to
+    -- the entity IO)
 
   . -- Pipeline registers
     SIGNAL in_data_p     : ...
@@ -135,8 +141,9 @@ Implementation steps:
       -- State variable
       VARIABLE v : t_reg;
       -- Auxiliary variables
-      VARIABLE v_*   -- optional, use to improve code readability
-                     -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ?
+      --VARIABLE v_*   -- optional, use to improve code readability
+      --               -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ?
+      VARIABLE w : t_comb;
     BEGIN
       v := r;      -- default keep existing state
       v.* := ...;  -- default force specific values, e.g. set strobes to '0',
@@ -152,7 +159,7 @@ Implementation steps:
       nxt_r <= v;
 
       -- memory less signals, only for view in wave window
-      s <= d;
+      dbg_wires <= w;
     END PROCESS;
 
   . -- Pipelining

libraries/base/dp/src/vhdl/dp_block_from_mm.vhd

@@ -124,7 +124,11 @@ BEGIN
     IF r.busy = '0' AND start_pulse = '1' THEN
       -- initiate next block
       v.busy := '1';
-    ELSIF r.busy = '1' THEN
+    END IF;
+
+    -- use v.busy, instead of r.busy, to allow start_pulse at mm_done, to
+    -- support zero gaps between output blocks
+    IF v.busy = '1' THEN
       IF out_siso.ready = '1' THEN
         -- continue with block
         mm_mosi.rd <= '1';

libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd

@@ -26,13 +26,17 @@
 --   input stream that is ahead of the other remote input streams. After a
 --   certain number of blocks on input 0, the same block on all remote
 --   inputs should also have arrived. If not then they are replaced by
---   replacement data. The output streams are paced by the block rate of input 0.
---   The user has to read the block within the block period.
+--   replacement data. The output streams are paced by the block rate of
+--   input 0. The user has to read the block within the block period.
 --
 --   Features:
---   . uses lost_data flag and replacement data to replace lost input blocks
+--   . The g_block_size <= block period, so supports input blocks arriving
+--     with or without data valid gaps
+--   . uses replacement data to replace lost input blocks and channel bit 0 as
+--     lost_data flag
 --   . uses replacement data to replace disabled input streams
---   . output block can be read in arbitrary order
+--   . output block can be read in arbitrary order via g_use_mm_output = TRUE
+--   . output block can be streamed via g_use_mm_output = FALSE
 --
 --   For more detailed description see:
 --   https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+aligner+v2
@@ -53,22 +57,23 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY dp_bsn_align_v2 IS
   GENERIC (
-    g_nof_streams                : NATURAL;           -- number of input and output streams
-    g_bsn_latency_max            : NATURAL;           -- Maximum travel latency of a remote block in number of block periods T_blk
+    g_nof_streams                : NATURAL;           -- >= 2, number of input and output streams
+    g_bsn_latency_max            : NATURAL;           -- maximum travel latency of a remote block in number of block periods T_blk
     g_nof_aligners_max           : POSITIVE := 1;     -- 1 when only align at last node, > 1 when align at every intermediate node
     g_block_size                 : NATURAL := 32;     -- > 1, g_block_size=1 is not supported
     g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
     g_data_w                     : NATURAL;           -- number of bits in sosi data
-    g_replacement_value          : INTEGER := 0;      -- output sosi data value for missing input blocks
+    g_data_replacement_value     : INTEGER := 0;      -- output sosi data value for missing input blocks
     g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
-    g_pipeline_input             : NATURAL := 0;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure
-    g_rd_latency                 : NATURAL := 1       -- 1 or 2, choose 2 to ease timing closure
+    g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+    g_pipeline_output            : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
+    g_rd_latency                 : NATURAL := 2       -- 1 or 2, choose 2 to ease timing closure
   );
   PORT (
     dp_rst         : IN  STD_LOGIC;
     dp_clk         : IN  STD_LOGIC;
 
-    node_index     : IN  NATURAL RANGE 0 TO g_nof_aligners_max := 0;  -- only used when g_nof_aligners_max > 1
+    node_index     : IN  NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0;  -- only used when g_nof_aligners_max > 1
 
     -- MM control
     stream_en_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1');
@@ -89,8 +94,8 @@ END dp_bsn_align_v2;
 
 ARCHITECTURE rtl OF dp_bsn_align_v2 IS
 
-  -- Circular buffer per stream
-  CONSTANT c_buffer_nof_blocks : NATURAL :=  ceil_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
+  -- Circular buffer per stream, size is next power of 2 that fits
+  CONSTANT c_buffer_nof_blocks : NATURAL :=  true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
 
   CONSTANT c_ram_size       : NATURAL := c_buffer_nof_blocks * g_block_size;
   CONSTANT c_ram_buf        : t_c_mem := (latency  => 1,
@@ -107,13 +112,18 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
   -- avoid that synthesis may infer a too larger multiplier
   CONSTANT c_product_w      : NATURAL := c_blk_pointer_w + c_block_size_w;
 
+  -- Output on lost data flag via out_sosi_arr().channel bit 0
+  CONSTANT c_channel_w      : NATURAL := 1;
+
   TYPE t_bsn_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+  TYPE t_channel_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_channel_w-1 DOWNTO 0);
   TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
   TYPE t_filled_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_buffer_nof_blocks-1 DOWNTO 0);
 
+  -- State
   TYPE t_reg IS RECORD
     -- p_write_arr
-    wr_pointer           : NATURAL;
+    wr_blk_pointer       : NATURAL;
     wr_copi_arr          : t_mem_copi_arr(g_nof_streams-1 DOWNTO 0);
     -- all streams
     filled_arr           : t_filled_arr(g_nof_streams-1 DOWNTO 0);
@@ -124,18 +134,24 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
     mm_sosi              : t_dp_sosi;
     dp_sosi              : t_dp_sosi;
     -- p_read
-    rd_pointer           : INTEGER;  -- use integer to detect need to wrap to natural
+    rd_blk_pointer       : INTEGER;  -- use integer to detect need to wrap to natural
     rd_offset            : STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
     rd_copi              : t_mem_copi;
     fill_cipo_arr        : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);  -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
-    out_bsn              : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);  -- hold BSN for streaming output
+    out_bsn              : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);  -- hold BSN until next sop, for easy view in Wave window
+    out_channel_arr      : t_channel_arr(g_nof_streams-1 DOWNTO 0);  -- hold channel until next sop per stream, for easy view in Wave window
   END RECORD;
 
+  -- Wires and auxiliary variables in p_comb
+  -- . For unique representation as signal wire, the p_comb should assign each
+  --   field in t_comb only once to a variable. It is allowed to reasign a
+  --   t_comb variable in p_comb, but then only the last assignment value will
+  --   be visible via the signal dbg_wires in the Wave window.
   TYPE t_comb IS RECORD
     ref_sosi            : t_dp_sosi;
-    pointer_slv       : STD_LOGIC_VECTOR(c_blk_pointer_w-1 DOWNTO 0);
+    blk_pointer_slv     : STD_LOGIC_VECTOR(c_blk_pointer_w-1 DOWNTO 0);
     product_slv         : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0);
-    lost_data_flag    : STD_LOGIC;
+    lost_data_flags_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
     out_sosi_arr        : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
   END RECORD;
 
@@ -151,14 +167,15 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
                                   (OTHERS=>'0'),
                                   c_mem_copi_rst,
                                   (OTHERS=>c_mem_cipo_rst),
-                                  (OTHERS=>'0'));
+                                  (OTHERS=>'0'),
+                                  (OTHERS=>(OTHERS=>'0')));
 
   -- State registers for p_comb
   SIGNAL r                 : t_reg;
   SIGNAL nxt_r             : t_reg;
 
-  -- Memoryless signals in p_comb (wires used as local auxiliary variables)
-  SIGNAL s             : t_comb;
+  -- Memoryless signals in p_comb (wires used as local variables)
+  SIGNAL dbg_wires         : t_comb;
 
   -- Structural signals (wires used to connect components and IO)
   SIGNAL dp_done           : STD_LOGIC;
@@ -172,6 +189,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
   -- Pipeline registers
   SIGNAL in_sosi_arr_p     : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL rd_copi           : t_mem_copi;
+  SIGNAL comb_out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
 
   -- Debug signals
   SIGNAL dbg_nof_streams            : NATURAL := g_nof_streams;
@@ -180,7 +198,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
   SIGNAL dbg_block_size             : NATURAL := g_block_size;
   SIGNAL dbg_bsn_w                  : NATURAL := g_bsn_w;
   SIGNAL dbg_data_w                 : NATURAL := g_data_w;
-  SIGNAL dbg_replacement_value   : INTEGER := g_replacement_value;
+  SIGNAL dbg_data_replacement_value : INTEGER := g_data_replacement_value;
   SIGNAL dbg_use_mm_output          : BOOLEAN := g_use_mm_output;
   SIGNAL dbg_pipeline_input         : NATURAL := g_pipeline_input;
   SIGNAL dbg_rd_latency             : NATURAL := g_rd_latency;
@@ -189,7 +207,8 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
 
 BEGIN
 
-  mm_sosi <= r.mm_sosi WHEN g_use_mm_output = TRUE ELSE c_dp_sosi_rst;
+  -- Output mm_sosi, also when g_use_mm_output = FALSE.
+  mm_sosi <= r.mm_sosi;
 
   p_reg : PROCESS(dp_clk, dp_rst)
   BEGIN
@@ -202,7 +221,7 @@ BEGIN
   
   p_comb : PROCESS(r, in_sosi_arr_p, mm_copi, dp_copi, rd_cipo_arr, rd_sosi_arr)
     VARIABLE v : t_reg;   -- State variable
-    VARIABLE d : t_comb;  -- Memoryless auxiliary variables, local wires
+    VARIABLE w : t_comb;  -- Local wires = memoryless auxiliary variables
   BEGIN
     v := r;  -- state signals
     v.mm_sosi := func_dp_stream_reset_control(r.mm_sosi);
@@ -222,56 +241,57 @@ BEGIN
 
       IF in_sosi_arr_p(I).sop = '1' THEN
         -- . set address at start of block
-        d.pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0);
-        d.product_slv := MULT_UVEC(d.pointer_slv, c_block_size_slv);
-        v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(d.product_slv);
+        w.blk_pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0);
+        w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
+        v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(w.product_slv);
 
         -- . set filled flag at sop, so assume rest of block will follow in time
-        v.filled_arr(I)(TO_UINT(d.pointer_slv)) := '1';
+        v.filled_arr(I)(TO_UINT(w.blk_pointer_slv)) := '1';
       END IF;
     END LOOP;
 
     ----------------------------------------------------------------------------
     -- p_control, all at sop of local reference input 0
     ----------------------------------------------------------------------------
-    d.ref_sosi := in_sosi_arr_p(0);
-    IF d.ref_sosi.sop = '1' THEN
+    w.ref_sosi := in_sosi_arr_p(0);
+    IF w.ref_sosi.sop = '1' THEN
       -- . write sync & bsn buffer
-      v.wr_pointer := TO_UINT(d.ref_sosi.bsn(c_blk_pointer_w-1 DOWNTO 0));
-      v.sync_arr(v.wr_pointer) := d.ref_sosi.sync;
-      v.bsn_arr(v.wr_pointer) := d.ref_sosi.bsn(g_bsn_w-1 DOWNTO 0);
-
-      -- . update read block pointer at g_bsn_latency_max blocks behind the reference write pointer
-      IF g_nof_aligners_max = 1 THEN
-        v.rd_pointer := v.wr_pointer - g_bsn_latency_max;
-      ELSE
-        v.rd_pointer := v.wr_pointer - g_bsn_latency_max * node_index;
-      END IF;
-      IF v.rd_pointer < 0 THEN
-        v.rd_pointer := v.rd_pointer + c_buffer_nof_blocks;
+      v.wr_blk_pointer := TO_UINT(w.ref_sosi.bsn(c_blk_pointer_w-1 DOWNTO 0));
+      v.sync_arr(v.wr_blk_pointer) := w.ref_sosi.sync;
+      v.bsn_arr(v.wr_blk_pointer) := w.ref_sosi.bsn(g_bsn_w-1 DOWNTO 0);
+
+      -- . update read block pointer at g_bsn_latency_max blocks behind the
+      --   reference write pointer, dependent on the node_index. For
+      --   g_bsn_latency_max = 1 the node_index = 0 fixed. For
+      --   g_bsn_latency_max > 1, node_index is the first BSN aligner in a
+      --   chain. Each subsequent node in the chain then has to account for
+      --   g_bsn_latency_max additional block latency.
+      v.rd_blk_pointer := v.wr_blk_pointer - g_bsn_latency_max * (1 + node_index);
+      IF v.rd_blk_pointer < 0 THEN
+        v.rd_blk_pointer := v.rd_blk_pointer + c_buffer_nof_blocks;
       END IF;
 
       -- . update read address of read block pointer
-      d.pointer_slv := TO_UVEC(v.rd_pointer, c_blk_pointer_w);
-      d.product_slv := MULT_UVEC(d.pointer_slv, c_block_size_slv);
-      v.rd_offset := RESIZE_UVEC(d.product_slv, c_mem_ram.adr_w);
+      w.blk_pointer_slv := TO_UVEC(v.rd_blk_pointer, c_blk_pointer_w);
+      w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
+      v.rd_offset := RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w);
 
       -- . issue mm_sosi, if there is output ready to be read, indicated by filled reference block
-      IF r.filled_arr(0)(v.rd_pointer) = '1' THEN
+      IF r.filled_arr(0)(v.rd_blk_pointer) = '1' THEN
         v.mm_sosi.sop := '1';
         v.mm_sosi.eop := '1';
         v.mm_sosi.valid := '1';
         -- . pass on timestamp information
-        v.mm_sosi.sync := v.sync_arr(v.rd_pointer);
-        v.mm_sosi.bsn := RESIZE_DP_BSN(v.bsn_arr(v.rd_pointer));
+        v.mm_sosi.sync := v.sync_arr(v.rd_blk_pointer);
+        v.mm_sosi.bsn := RESIZE_DP_BSN(v.bsn_arr(v.rd_blk_pointer));
         -- . pass on lost data flags for enabled streams via channel field, and
         --   determine whether the ouput has to insert replacement data
         v.mm_sosi.channel := (OTHERS=>'0');
         FOR I IN 0 TO g_nof_streams-1 LOOP
-          d.lost_data_flag := NOT v.filled_arr(I)(v.rd_pointer);
+          w.lost_data_flags_arr(I) := NOT v.filled_arr(I)(v.rd_blk_pointer);
           IF stream_en_arr(I) = '1' THEN  -- use MM bit at sop
-            v.use_replacement_data(I) := d.lost_data_flag;  -- enabled stream, so replace the data if the data was lost
-            v.mm_sosi.channel(I) := d.lost_data_flag;  -- enabled stream, so flag the data if the data was lost
+            v.use_replacement_data(I) := w.lost_data_flags_arr(I);  -- enabled stream, so replace the data if the data was lost
+            v.mm_sosi.channel(I) := w.lost_data_flags_arr(I);  -- enabled stream, so flag the data if the data was lost
           ELSE
             v.use_replacement_data(I) := '1';  -- disabled stream, so replace the data, but do not flag the data as lost
           END IF;
@@ -280,7 +300,7 @@ BEGIN
 
       -- . clear filled flags, after mm_sosi was issued, or could have been issued
       FOR I IN 0 TO g_nof_streams-1 LOOP
-        v.filled_arr(I)(v.rd_pointer) := '0';
+        v.filled_arr(I)(v.rd_blk_pointer) := '0';
       END LOOP;
     END IF;
 
@@ -294,7 +314,7 @@ BEGIN
     -- . if necessary, replace a stream by replacement data
     FOR I IN 0 TO g_nof_streams-1 LOOP
       IF r.use_replacement_data(I) = '1' THEN
-        v.fill_cipo_arr(I).rddata := TO_MEM_SDATA(g_replacement_value);
+        v.fill_cipo_arr(I).rddata := TO_MEM_SDATA(g_data_replacement_value);
       END IF;
     END LOOP;
 
@@ -311,7 +331,7 @@ BEGIN
       mm_cipo_arr <= v.fill_cipo_arr;
 
       -- . no output via DP streaming interface
-      out_sosi_arr <= (OTHERS => c_dp_sosi_rst);
+      comb_out_sosi_arr <= (OTHERS => c_dp_sosi_rst);
     ELSE
       --------------------------------------------------------------------------
       -- Do the output via the DP streaming interface
@@ -327,26 +347,33 @@ BEGIN
       END IF;
 
       -- . pass on input data from the buffer
-      d.out_sosi_arr := rd_sosi_arr;  -- = v.fill_cipo_arr in streaming format, contains the
+      w.out_sosi_arr := rd_sosi_arr;  -- = v.fill_cipo_arr in streaming format, contains the
                                       -- input data from the buffer or replacement data
       IF rd_sosi_arr(0).sop = '1' THEN
         -- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr
-        d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.dp_sosi.sync, "SYNC");
-        d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.dp_sosi.bsn, "BSN");
+        w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.sync, "SYNC");
+        w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.bsn, "BSN");
         FOR I IN 0 TO g_nof_streams-1 LOOP
           -- . pass on the lost flag per stream
-          d.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(slv(r.dp_sosi.channel(I)));
+          w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(slv(r.dp_sosi.channel(I)));
         END LOOP;
 
-        -- . hold BSN until next sop, to ease view in wave window
+        -- . hold sop info fields until next sop, to ease view in wave window
         v.out_bsn := r.dp_sosi.bsn(g_bsn_w-1 DOWNTO 0);
+        FOR I IN 0 TO g_nof_streams-1 LOOP
+          v.out_channel_arr(I) := w.out_sosi_arr(I).channel(c_channel_w-1 DOWNTO 0);
+        END LOOP;
       ELSE
-        -- . until next sop pass on BSN, to ease view in wave window
-        d.out_sosi_arr := func_dp_stream_arr_set(d.out_sosi_arr, r.out_bsn, "BSN");
+        -- . until next sop pass on BSN to all streams, to ease view in wave window
+        w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.out_bsn, "BSN");
+        FOR I IN 0 TO g_nof_streams-1 LOOP
+           -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
+           w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
+        END LOOP;
       END IF;
 
       -- . output via DP streaming interface
-      out_sosi_arr <= d.out_sosi_arr;
+      comb_out_sosi_arr <= w.out_sosi_arr;
 
       -- . no output via MM interface
       mm_cipo_arr <= (OTHERS => c_mem_cipo_rst);
@@ -357,8 +384,8 @@ BEGIN
     ----------------------------------------------------------------------------
     nxt_r <= v;
 
-    -- memory less signals, only for view in wave window
-    s <= d;
+    -- local wires, only for view in wave window
+    dbg_wires <= w;
   END PROCESS;
 
   ------------------------------------------------------------------------------
@@ -421,7 +448,7 @@ BEGIN
   -- Pipelining
   ------------------------------------------------------------------------------
 
-  -- . input
+  -- . input streams
   u_in_sosi_arr_p : ENTITY work.dp_pipeline_arr
   GENERIC MAP (
     g_nof_streams => g_nof_streams,
@@ -439,4 +466,19 @@ BEGIN
   -- . read RAM
   rd_copi <= nxt_r.rd_copi WHEN g_rd_latency = 1 ELSE r.rd_copi;
 
+  -- . output streams
+  u_out_sosi_arr_p : ENTITY work.dp_pipeline_arr
+  GENERIC MAP (
+    g_nof_streams => g_nof_streams,
+    g_pipeline    => g_pipeline_output
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    -- ST sink
+    snk_in_arr   => comb_out_sosi_arr,
+    -- ST source
+    src_out_arr  => out_sosi_arr
+  );
+
 END rtl;

libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd

@@ -43,13 +43,19 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY mmp_dp_bsn_align_v2 IS
   GENERIC (
+    -- for dp_bsn_align_v2
     g_nof_streams                : NATURAL;           -- number of input and output streams
     g_bsn_latency_max            : NATURAL;           -- Maximum travel latency of a remote block in number of block periods T_blk
     g_nof_aligners_max           : NATURAL := 1;      -- 1 when only align at last node, > 1 when align at every intermediate node
     g_block_size                 : NATURAL := 32;     -- > 1, g_block_size=1 is not supported
     g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
     g_data_w                     : NATURAL;           -- number of bits in sosi data
-    g_replacement_value          : INTEGER := 0;      -- output sosi data value for missing input blocks
+    g_data_replacement_value     : INTEGER := 0;      -- output sosi data value for missing input blocks
+    g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
+    g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+    g_pipeline_output            : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
+    g_rd_latency                 : NATURAL := 2;      -- 1 or 2, choose 2 to ease timing closure
+    -- for mms_dp_bsn_monitor_v2
     g_nof_clk_per_sync           : NATURAL := 200*10**6;
     g_nof_input_bsn_monitors     : NATURAL := 0;
     g_use_bsn_output_monitor     : BOOLEAN := FALSE
@@ -59,8 +65,8 @@ ENTITY mmp_dp_bsn_align_v2 IS
     mm_rst                  : IN  STD_LOGIC;
     mm_clk                  : IN  STD_LOGIC;
 
-    reg_copi                : IN  t_mem_copi;
-    reg_cipo                : OUT t_mem_cipo;
+    reg_bsn_align_copi      : IN  t_mem_copi;
+    reg_bsn_align_cipo      : OUT t_mem_cipo;
 
     reg_input_monitor_copi  : IN  t_mem_copi;
     reg_input_monitor_cipo  : OUT t_mem_cipo;
@@ -72,15 +78,18 @@ ENTITY mmp_dp_bsn_align_v2 IS
     dp_rst                  : IN  STD_LOGIC;
     dp_clk                  : IN  STD_LOGIC;
 
-    node_index     : IN  NATURAL := 0;  -- only used when g_nof_aligners_max > 1
+    node_index              : IN  NATURAL RANGE 0 TO g_nof_aligners_max-1 := 0;  -- only used when g_nof_aligners_max > 1
 
     -- Streaming input
     in_sosi_arr             : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
 
-    -- Output via local MM in dp_clk domain
-    mm_copi        : IN  t_mem_copi;  -- read access to output block, all output streams share same mm_copi
+    -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
+    mm_sosi                 : OUT t_dp_sosi;   -- streaming information that signals that an output block can be read
+    mm_copi                 : IN  t_mem_copi := c_mem_copi_rst;  -- read access to output block, all output streams share same mm_copi
     mm_cipo_arr             : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);
-    mm_sosi        : OUT t_dp_sosi   -- streaming information that signals that an output block can be read
+
+    -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+    out_sosi_arr            : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
   );
 END mmp_dp_bsn_align_v2;
 
@@ -100,10 +109,14 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS
   SIGNAL reg_wr           : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
   SIGNAL stream_en_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
-  SIGNAL mm_sosi_arr    : t_dp_sosi_arr(0 DOWNTO 0);
+  SIGNAL ref_sync         : STD_LOGIC;
+  SIGNAL mon_out_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
+  SIGNAL i_out_sosi_arr   : t_dp_sosi_arr(g_nof_streams-1  DOWNTO 0);
+  SIGNAL i_mm_sosi        : t_dp_sosi;
 
 BEGIN
 
+  -- MM control of BSN aligner
   u_reg : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (
     g_cross_clock_domain   => TRUE,
@@ -118,8 +131,8 @@ BEGIN
     st_clk         => dp_clk,
 
     -- Memory Mapped Slave in mm_clk domain
-    sla_in         => reg_copi,
-    sla_out        => reg_cipo,
+    sla_in         => reg_bsn_align_copi,
+    sla_out        => reg_bsn_align_cipo,
 
     -- MM registers in st_clk domain
     reg_wr_arr     => OPEN,
@@ -130,6 +143,9 @@ BEGIN
 
   stream_en_arr <= reg_wr;
 
+  -- Use local sync as reference sync input for the BSN monitors
+  ref_sync <= in_sosi_arr(0).sync;
+
   -- Use input BSN monitors for the first g_nof_input_bsn_monitors input
   -- streams, e.g. to support:
   -- . only one input stream (g_nof_input_bsn_monitors = 1), or
@@ -156,9 +172,8 @@ BEGIN
       -- Streaming clock domain
       dp_rst         => dp_rst,
       dp_clk         => dp_clk,
-      ref_sync       => in_sosi_arr(0).sync,  -- local reference sync input
+      ref_sync       => ref_sync,
 
-      in_siso_arr    => (OTHERS=>c_dp_siso_rdy),
       in_sosi_arr    => in_sosi_arr(g_nof_input_bsn_monitors-1 DOWNTO 0)
     );
   END GENERATE;
@@ -185,13 +200,19 @@ BEGIN
       -- Streaming clock domain
       dp_rst         => dp_rst,
       dp_clk         => dp_clk,
-      ref_sync       => in_sosi_arr(0).sync,  -- local reference sync input
+      ref_sync       => ref_sync,
 
-      in_siso_arr    => (OTHERS=>c_dp_siso_rdy),
-      in_sosi_arr    => mm_sosi_arr
+      in_sosi_arr    => mon_out_sosi_arr
     );
   END GENERATE;
 
+  -- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor
+  mon_out_sosi_arr(0) <= i_mm_sosi WHEN g_use_mm_output = TRUE ELSE i_out_sosi_arr(0);
+
+  -- wire to output
+  mm_sosi <= i_mm_sosi;
+  out_sosi_arr <= i_out_sosi_arr;
+
   u_bsn_align : ENTITY work.dp_bsn_align_v2
   GENERIC MAP (
     g_nof_streams                => g_nof_streams,
@@ -200,7 +221,11 @@ BEGIN
     g_block_size                 => g_block_size,
     g_bsn_w                      => g_bsn_w,
     g_data_w                     => g_data_w,
-    g_replacement_value          => g_replacement_value
+    g_data_replacement_value     => g_data_replacement_value,
+    g_use_mm_output              => g_use_mm_output,
+    g_pipeline_input             => g_pipeline_input,
+    g_pipeline_output            => g_pipeline_output,
+    g_rd_latency                 => g_rd_latency
   )
   PORT MAP (
     dp_rst         => dp_rst,
@@ -211,12 +236,12 @@ BEGIN
     -- Streaming input
     in_sosi_arr    => in_sosi_arr,
     -- Output via local MM in dp_clk domain
+    mm_sosi        => i_mm_sosi,
     mm_copi        => mm_copi,
     mm_cipo_arr    => mm_cipo_arr,
-    mm_sosi        => mm_sosi
+    -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+    out_sosi_arr   => i_out_sosi_arr
   );
 
-  mm_sosi <= mm_sosi_arr(0);
-
 END str;
 

libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd

@@ -34,10 +34,9 @@ END tb_tb_dp_bsn_align_v2;
 
 ARCHITECTURE tb OF tb_tb_dp_bsn_align_v2 IS
 
-  CONSTANT c_bsn_latency_max      : POSITIVE := 1;
   CONSTANT c_block                : NATURAL := 11;
   CONSTANT c_period               : NATURAL := 20;
-  CONSTANT c_delay_max            : NATURAL := c_bsn_latency_max * c_period;
+  CONSTANT c_nof_blk              : NATURAL := 30;
 
   SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 
@@ -51,20 +50,35 @@ BEGIN
   -- g_block_period               : NATURAL := 20;     -- >= g_block_size, = g_block_size + c_gap_size
   -- g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
   -- g_data_w                     : NATURAL := 16;     -- number of bits in sosi data
-  -- c_replacement_value          : INTEGER := 0;      -- output sosi data replacement value for missing input blocks
+  -- g_data_replacement_value     : INTEGER := 0;      -- output sosi data replacement value for missing input blocks
+  -- g_disable_stream_id          : NATURAL := 0;      -- default 0 to enable all streams, > 0 selects stream that will be disabled
+  -- g_lost_stream_id             : NATURAL := 0;      -- default 0 to have all streams, > 0 selects stream that will be lost
+  -- g_lost_bsn_id                : NATURAL := 10;     -- for stream 1 the block with bsn = g_lost_bsn_id will be lost
   -- g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
-  -- g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure
+  -- g_pipeline_input             : NATURAL := 0;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+  -- g_pipeline_output            : NATURAL := 0;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sop_arr
   -- g_rd_latency                 : NATURAL := 2;      -- 1 or 2, choose 2 to ease timing closure
   --
   -- -- TB
-  -- g_tb_diff_delay_max    : NATURAL := 45;      -- maximum nof clk delay between any inputs, <= c_align_latency
+  -- g_tb_diff_delay        : INTEGER := 0;       -- 0 = aligned inputs, -1 = max input delay for no loss,
+  --                                              -- >~ g_bsn_latency_max * g_block_period will give loss
   -- g_tb_nof_restart       : NATURAL := 1;       -- number of times to restart the input stimuli
   -- g_tb_nof_blocks        : NATURAL := 10       -- number of input blocks per restart
 
-  u_mm_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17,  TRUE, 0, 1,                0, 1, 50);
-  u_dp_output          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1,                0, 1, 50);
-
-  u_diff_delay_no_loss : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1,      c_delay_max, 1, 50);
-  --u_loss_replacement   : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, c_block, c_period, 32, 16, 17, FALSE, 0, 1, 40 + c_delay_max, 1, 50);
+  u_mm_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0,  TRUE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_dp_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_dp_output_p1            : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 1, 1, 1,  0, 2, c_nof_blk);
+  u_bsn_lat_max_2           : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 2, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_bsn_lat_max_3           : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 3, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_p1_rd2                  : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 1, 0, 2,  0, 2, c_nof_blk);
+  u_zero_gap                : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block,  c_block, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_zero_gap_p1_rd2         : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block,  c_block, 32, 16, 17, 0, 0,  0, FALSE, 1, 1, 2,  0, 2, c_nof_blk);
+  u_stream_disable          : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 2, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_stream_lost             : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 2,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_stream_disable_lost     : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (4, 1, 1, c_block, c_period, 32, 16, 17, 1, 2,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_bsn_lost                : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 10, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_diff_delay              : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1, -1, 2, c_nof_blk);
+  u_nof_aligners            : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 8, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_nof_aligners_diff_delay : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (4, 1, 3, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1, -1, 2, c_nof_blk);
 
 END tb;