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Commit e78d2207 authored by Eric Kooistra's avatar Eric Kooistra
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Corrected Wait for protocol ready.

parent 002f0e41
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...@@ -209,12 +209,17 @@ BEGIN ...@@ -209,12 +209,17 @@ BEGIN
proc_mem_mm_bus_wr(0, c_control_activate, clk, control_miso, control_mosi); proc_mem_mm_bus_wr(0, c_control_activate, clk, control_miso, control_mosi);
-- Wait for protocol ready -- Wait for protocol ready
WHILE control_status='0' LOOP -- . wait for control_interrupt
proc_mem_mm_bus_rd(0, clk, control_miso, control_mosi); -- read result available in control_status -- . do not use control_mosi to poll control_status, because then it can just occur that the read
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk); -- that act as acknowledge again clears the control_status before it got noticed in the
control_status <= control_miso.rddata(c_control_ready_bi); -- WHILE control_status='0' LOOP
proc_common_wait_some_cycles(clk, 1); proc_common_wait_until_high(clk, control_interrupt);
END LOOP; --WHILE control_status='0' LOOP
proc_mem_mm_bus_rd(0, clk, control_miso, control_mosi); -- read result available in control_status
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, clk);
control_status <= control_miso.rddata(c_control_ready_bi);
proc_common_wait_some_cycles(clk, 1);
--END LOOP;
-- Read result list -- Read result list
FOR I IN 0 TO c_expected_mask'LENGTH-1 LOOP FOR I IN 0 TO c_expected_mask'LENGTH-1 LOOP
......
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