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Commit e65f0796 authored by Eric Kooistra's avatar Eric Kooistra
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Use tech_iobuf component in common_ddio.

parent a5bf7ba9
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hdl_lib_name = common hdl_lib_name = common
hdl_library_clause_name = common_lib hdl_library_clause_name = common_lib
hdl_lib_uses = technology tech_memory tech_fifo tst hdl_lib_uses = technology tech_memory tech_fifo tech_iobuf tst
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = build_synth_dir =
...@@ -45,13 +45,12 @@ synth_files = ...@@ -45,13 +45,12 @@ synth_files =
src/vhdl/common_fifo_dc.vhd src/vhdl/common_fifo_dc.vhd
src/vhdl/common_fifo_dc_mixed_widths.vhd src/vhdl/common_fifo_dc_mixed_widths.vhd
src/vhdl/common_ddio_in.vhd
src/vhdl/common_ddio_out.vhd
$UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd $UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd $UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd $UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddio_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddio_in_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddio_out.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddio_out_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_inout.vhd $UNB/Firmware/modules/common/src/vhdl/common_inout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd $UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd $UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd
......
...@@ -21,12 +21,13 @@ ...@@ -21,12 +21,13 @@
-- Purpose: Capture double data rate FPGA input -- Purpose: Capture double data rate FPGA input
LIBRARY IEEE; LIBRARY IEEE, technology_lib, tech_iobuf_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ddio_in IS ENTITY common_ddio_in IS
GENERIC( GENERIC(
g_device_family : STRING := "Stratix IV"; g_technology : NATURAL := c_tech_select_default;
g_width : NATURAL := 1 g_width : NATURAL := 1
); );
PORT ( PORT (
...@@ -38,3 +39,23 @@ ENTITY common_ddio_in IS ...@@ -38,3 +39,23 @@ ENTITY common_ddio_in IS
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0) out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
); );
END common_ddio_in; END common_ddio_in;
ARCHITECTURE str OF common_ddio_in IS
BEGIN
u_ddio_in : ENTITY tech_iobuf_lib.tech_iobuf_ddio_in
GENERIC MAP (
g_technology => g_technology,
g_width => g_width
)
PORT MAP (
in_dat => in_dat,
in_clk => in_clk,
in_clk_en => in_clk_en,
rst => rst,
out_dat_hi => out_dat_hi,
out_dat_lo => out_dat_lo
);
END str;
...@@ -21,12 +21,13 @@ ...@@ -21,12 +21,13 @@
-- Purpose: Double data rate FPGA output or register single data rate FPGA output -- Purpose: Double data rate FPGA output or register single data rate FPGA output
LIBRARY IEEE; LIBRARY IEEE, technology_lib, tech_iobuf_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ddio_out IS ENTITY common_ddio_out IS
GENERIC( GENERIC(
g_device_family : STRING := "Stratix IV"; g_technology : NATURAL := c_tech_select_default;
g_width : NATURAL := 1 g_width : NATURAL := 1
); );
PORT ( PORT (
...@@ -38,3 +39,23 @@ ENTITY common_ddio_out IS ...@@ -38,3 +39,23 @@ ENTITY common_ddio_out IS
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0) out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
); );
END common_ddio_out; END common_ddio_out;
ARCHITECTURE str OF common_ddio_out IS
BEGIN
u_ddio_out : ENTITY tech_iobuf_lib.tech_iobuf_ddio_out
GENERIC MAP (
g_technology => g_technology,
g_width => g_width
)
PORT MAP (
rst => rst,
in_clk => in_clk,
in_clk_en => in_clk_en,
in_dat_hi => in_dat_hi,
in_dat_lo => in_dat_lo,
out_dat => out_dat
);
END str;
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