From e65f07967c7d9383df65b6b2a6932f188d007797 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 27 May 2014 13:27:45 +0000
Subject: [PATCH] Use tech_iobuf component in common_ddio.
---
libraries/base/common/hdllib.cfg | 9 +++----
.../base/common/src/vhdl/common_ddio_in.vhd | 27 ++++++++++++++++---
.../base/common/src/vhdl/common_ddio_out.vhd | 27 ++++++++++++++++---
3 files changed, 52 insertions(+), 11 deletions(-)
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index fde6fb7325..7e3305c361 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = common
hdl_library_clause_name = common_lib
-hdl_lib_uses = technology tech_memory tech_fifo tst
+hdl_lib_uses = technology tech_memory tech_fifo tech_iobuf tst
build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
@@ -45,13 +45,12 @@ synth_files =
src/vhdl/common_fifo_dc.vhd
src/vhdl/common_fifo_dc_mixed_widths.vhd
+ src/vhdl/common_ddio_in.vhd
+ src/vhdl/common_ddio_out.vhd
+
$UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
- $UNB/Firmware/modules/common/src/vhdl/common_ddio_in.vhd
- $UNB/Firmware/modules/common/src/vhdl/common_ddio_in_a_stratix4.vhd
- $UNB/Firmware/modules/common/src/vhdl/common_ddio_out.vhd
- $UNB/Firmware/modules/common/src/vhdl/common_ddio_out_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_inout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd
diff --git a/libraries/base/common/src/vhdl/common_ddio_in.vhd b/libraries/base/common/src/vhdl/common_ddio_in.vhd
index c7e99225c7..f98b0f7a94 100644
--- a/libraries/base/common/src/vhdl/common_ddio_in.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_in.vhd
@@ -21,13 +21,14 @@
-- Purpose: Capture double data rate FPGA input
-LIBRARY IEEE;
+LIBRARY IEEE, technology_lib, tech_iobuf_lib;
USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ddio_in IS
GENERIC(
- g_device_family : STRING := "Stratix IV";
- g_width : NATURAL := 1
+ g_technology : NATURAL := c_tech_select_default;
+ g_width : NATURAL := 1
);
PORT (
in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
@@ -38,3 +39,23 @@ ENTITY common_ddio_in IS
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END common_ddio_in;
+
+
+ARCHITECTURE str OF common_ddio_in IS
+BEGIN
+
+ u_ddio_in : ENTITY tech_iobuf_lib.tech_iobuf_ddio_in
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ PORT MAP (
+ in_dat => in_dat,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ rst => rst,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
+
+END str;
diff --git a/libraries/base/common/src/vhdl/common_ddio_out.vhd b/libraries/base/common/src/vhdl/common_ddio_out.vhd
index 0f48ca1ce4..613e105932 100644
--- a/libraries/base/common/src/vhdl/common_ddio_out.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_out.vhd
@@ -21,13 +21,14 @@
-- Purpose: Double data rate FPGA output or register single data rate FPGA output
-LIBRARY IEEE;
+LIBRARY IEEE, technology_lib, tech_iobuf_lib;
USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ddio_out IS
GENERIC(
- g_device_family : STRING := "Stratix IV";
- g_width : NATURAL := 1
+ g_technology : NATURAL := c_tech_select_default;
+ g_width : NATURAL := 1
);
PORT (
rst : IN STD_LOGIC := '0';
@@ -38,3 +39,23 @@ ENTITY common_ddio_out IS
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END common_ddio_out;
+
+
+ARCHITECTURE str OF common_ddio_out IS
+BEGIN
+
+ u_ddio_out : ENTITY tech_iobuf_lib.tech_iobuf_ddio_out
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ PORT MAP (
+ rst => rst,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ in_dat_hi => in_dat_hi,
+ in_dat_lo => in_dat_lo,
+ out_dat => out_dat
+ );
+
+END str;
--
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