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Commit e5d3bcf4 authored by Zanting's avatar Zanting
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Added new ddr versions

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boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
+ 133
− 294
View file @ e5d3bcf4
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 -- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-- --
-- This program is free software: you can redistribute it and/or modify -- This program is free software: you can redistribute it and/or modify
...@@ -20,331 +19,171 @@ ...@@ -20,331 +19,171 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, diag_lib, io_ddr_lib, reorder_lib; LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL; USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL; USE diag_lib.diag_pkg.ALL;
USE reorder_lib.reorder_pkg.ALL; USE technology_lib.technology_select_pkg.ALL;
USE work.unb1_test_pkg.ALL; USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddr_stream IS ENTITY ddr_stream IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := FALSE; g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_stratixiv; g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL; g_tech_ddr : t_c_tech_ddr;
g_data_w : NATURAL; g_st_dat_w : NATURAL := 64 -- Any power of two 8..256
g_bg_block_size : NATURAL := 1024;
g_bg_gapsize : NATURAL := 0;
g_bg_blocks_per_sync : NATURAL := 200000;
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_ena_pre_transp : BOOLEAN := FALSE;
g_reorder_seq : t_reorder_seq := c_reorder_seq_same
); );
PORT ( PORT (
-- System -- System
mm_rst : IN STD_LOGIC; mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC; mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
-- blockgen mm
reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
reg_diag_bg_miso : OUT t_mem_miso;
ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
ram_diag_bg_miso : OUT t_mem_miso;
reg_diag_tx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- bsn
reg_bsn_monitor_mosi : IN t_mem_mosi;
reg_bsn_monitor_miso : OUT t_mem_miso;
-- databuffer
reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : OUT t_mem_miso;
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso;
reg_diag_rx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_rx_seq_miso : OUT t_mem_miso;
-- IO DDR register map
reg_io_ddr_mosi : IN t_mem_mosi;
reg_io_ddr_miso : OUT t_mem_miso;
-- Reorder transpose
ram_ss_ss_transp_mosi : IN t_mem_mosi;
ram_ss_ss_transp_miso : OUT t_mem_miso;
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END ddr_stream;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
ddr_ref_clk : IN STD_LOGIC;
ddr_ref_rst : IN STD_LOGIC;
ARCHITECTURE str OF ddr_stream IS -- Clock outputs
ddr_out_clk : OUT STD_LOGIC;
ddr_out_rst : OUT STD_LOGIC;
-- Block generator -- MM interface
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default) reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
'0', -- enable_sync reg_io_ddr_miso : OUT t_mem_miso;
TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size; -- Data Buffer Control
CONSTANT c_min_nof_words_per_block : NATURAL := 1; reg_diag_data_buf_mosi : IN t_mem_mosi;
CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1; reg_diag_data_buf_miso : OUT t_mem_miso;
-- Data Buffer Data
ram_diag_data_buf_mosi : IN t_mem_mosi;
ram_diag_data_buf_miso : OUT t_mem_miso;
-- ddr -- TX Sequencer
CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO. reg_diag_tx_seq_mosi : IN t_mem_mosi;
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO. reg_diag_tx_seq_miso : OUT t_mem_miso;
-- RX Sequencer
reg_diag_rx_seq_mosi : IN t_mem_mosi;
reg_diag_rx_seq_miso : OUT t_mem_miso;
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- DDR3 pass on termination control from master to slave controller
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy); term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL to_mem_sosi : t_dp_sosi;
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
SIGNAL ddr_ref_rst : STD_LOGIC;
SIGNAL ddr_out_clk_i : STD_LOGIC;
SIGNAL ddr_out_rst_i : STD_LOGIC;
BEGIN
----------------------------------------------------------------------------- -- SO-DIMM Memory Bank I = ddr3_I
-- TX: Block generator and DP fifo phy_3_in : IN t_tech_ddr3_phy_in;
----------------------------------------------------------------------------- phy_3_io : INOUT t_tech_ddr3_phy_io;
u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen phy_3_ou : OUT t_tech_ddr3_phy_ou
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_buf_dat_w => g_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_index_arr => array_init(0, g_nof_streams),
g_file_name_prefix => "hex/counter_data_" & NATURAL'IMAGE(g_data_w),
g_diag_block_gen_rst => c_bg_ctrl,
g_use_tx_seq => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => '1',
out_sosi_arr => block_gen_src_out_arr,
out_siso_arr => block_gen_src_in_arr,
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso
); );
END ddr_stream;
ARCHITECTURE str OF ddr_stream IS
u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor CONSTANT c_wr_data_w : NATURAL := g_st_dat_w;
GENERIC MAP ( CONSTANT c_rd_data_w : NATURAL := g_st_dat_w;
g_nof_streams => g_nof_streams, CONSTANT c_data_w : NATURAL := g_st_dat_w;
g_cross_clock_domain => TRUE,
--g_sync_timeout => g_bg_blocks_per_sync*(g_bg_block_size+g_bg_gapsize),
g_cnt_sop_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync+1),
g_cnt_valid_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync*g_bg_block_size+1),
g_log_first_bsn => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_mosi,
reg_miso => reg_bsn_monitor_miso,
dp_rst => dp_rst,
dp_clk => dp_clk,
in_siso_arr => diag_data_buf_snk_out_arr,
in_sosi_arr => diag_data_buf_snk_in_arr
);
diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => 32, --g_data_w, --FIXME
g_buf_nof_data => 1024,
g_buf_use_sync => FALSE, -- sync by reading last address of data buffer
g_use_rx_seq => TRUE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
u_transpose: ENTITY reorder_lib.reorder_transpose
GENERIC MAP(
g_nof_streams => g_nof_streams,
g_in_dat_w => g_data_w,
g_frame_size_in => g_reorder_seq.wr_chunksize,
g_frame_size_out => g_reorder_seq.wr_chunksize,
g_use_complex => FALSE,
g_ena_pre_transp => g_ena_pre_transp,
g_reorder_seq => g_reorder_seq
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => ddr_out_rst_i,
dp_clk => ddr_out_clk_i,
-- ST sink
snk_out_arr => block_gen_src_in_arr,
snk_in_arr => block_gen_src_out_arr,
-- ST source
src_in_arr => (OTHERS => c_dp_siso_rdy),
src_out_arr => diag_data_buf_snk_in_arr,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi, CONSTANT c_wr_fifo_depth : NATURAL := 1024; -- >=16 , defined at DDR side of the FIFO.
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso, CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
-- Control interface to the external memory CONSTANT c_use_bg : BOOLEAN := FALSE;
dvr_miso => ctlr_dvr_miso, CONSTANT c_use_tx_seq : BOOLEAN := TRUE;
dvr_mosi => ctlr_dvr_mosi, CONSTANT c_use_db : BOOLEAN := FALSE;
CONSTANT c_use_rx_seq : BOOLEAN := TRUE;
CONSTANT c_buf_nof_data : NATURAL := 1024;
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_seq_dat_w : NATURAL := 16;
-- Data interface to the external memory SIGNAL en_sync : STD_LOGIC;
to_mem_src_out => to_mem_sosi,
to_mem_src_in => to_mem_siso,
from_mem_snk_in => from_mem_sosi, SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
from_mem_snk_out => from_mem_siso SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- Output SOSI that contains the waveform data
SIGNAL in_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
); BEGIN
u_areset_ddr_ref_rst : ENTITY common_lib.common_areset u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP( GENERIC MAP(
g_rst_level => '1', -- System
g_delay_len => 40 g_technology => g_technology,
) g_dp_data_w => g_st_dat_w,
PORT MAP( g_dp_seq_dat_w => c_seq_dat_w,
clk => dp_clk, g_dp_wr_fifo_depth => c_wr_fifo_depth,
in_rst => '0', g_dp_rd_fifo_depth => c_rd_fifo_depth,
out_rst => ddr_ref_rst -- IO_DDR
); g_io_tech_ddr => g_tech_ddr,
-- DIAG data buffer
g_db_use_db => c_use_db,
g_db_buf_nof_data => c_buf_nof_data
)
PORT MAP(
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
---------------------------------------------------------------------------
-- DDR reference clock
ctlr_ref_clk => ddr_ref_clk,
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk,
ctlr_rst_out => ddr_out_rst,
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
wr_fifo_usedw => OPEN,
rd_fifo_usedw => OPEN,
-- DDR3 pass on termination control from master to slave controller
term_ctrl_out => term_ctrl_out,
term_ctrl_in => term_ctrl_in,
-- DDR3 PHY external interface
phy3_in => phy_3_in,
phy3_io => phy_3_io,
phy3_ou => phy_3_ou,
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
-- MM interface
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso,
---------------------------------------------------------------------------
-- DIAG rx seq with optional data buffer
---------------------------------------------------------------------------
-- MM interface
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso
);
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_technology => g_technology,
g_tech_ddr => g_tech_ddr,
g_cross_domain_dvr_ctlr => FALSE,
g_wr_data_w => g_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => g_data_w,
g_wr_flush_mode => "SYN",
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
g_wr_flush_nof_channels => 1
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-- MM register map for DDR controller status info
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- DDR reference clock
ctlr_ref_clk => dp_clk,
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk_i,
ctlr_rst_out => ddr_out_rst_i,
ctlr_clk_in => ddr_out_clk_i,
ctlr_rst_in => ddr_out_rst_i,
-- Driver clock domain
dvr_clk => ddr_out_clk_i,
dvr_rst => ddr_out_rst_i,
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain
wr_clk => ddr_out_clk_i,
wr_rst => ddr_out_rst_i,
wr_fifo_usedw => OPEN,
wr_sosi => to_mem_sosi,
wr_siso => to_mem_siso,
-- Read FIFO clock domain
rd_clk => ddr_out_clk_i,
rd_rst => ddr_out_rst_i,
rd_fifo_usedw => OPEN,
rd_sosi => from_mem_sosi,
rd_siso => from_mem_siso,
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
phy3_in => MB_I_IN,
phy3_io => MB_I_IO,
phy3_ou => MB_I_OU
);
END str; END str;
boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+ 71
− 66
View file @ e5d3bcf4
...@@ -28,7 +28,6 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -28,7 +28,6 @@ PACKAGE qsys_unb1_test_pkg IS
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
component qsys_unb1_test is component qsys_unb1_test is
port ( port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
...@@ -152,20 +151,6 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -152,20 +151,6 @@ PACKAGE qsys_unb1_test_pkg IS
reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_ss_ss_wide_read_export : out std_logic; -- export
ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_ss_ss_wide_write_export : out std_logic; -- export
ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
ram_ss_ss_wide_clk_export : out std_logic; -- export
ram_ss_ss_wide_reset_export : out std_logic; -- export
reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_io_ddr_read_export : out std_logic; -- export
reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_io_ddr_write_export : out std_logic; -- export
reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
reg_io_ddr_clk_export : out std_logic; -- export
reg_io_ddr_reset_export : out std_logic; -- export
reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
...@@ -271,55 +256,6 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -271,55 +256,6 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_ddr_read_export : out std_logic; -- export
reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_ddr_write_export : out std_logic; -- export
reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_bg_ddr_read_export : out std_logic; -- export
reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_bg_ddr_write_export : out std_logic; -- export
reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_bg_ddr_clk_export : out std_logic; -- export
reg_diag_bg_ddr_reset_export : out std_logic; -- export
ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_bg_ddr_read_export : out std_logic; -- export
ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_ddr_write_export : out std_logic; -- export
ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
ram_diag_bg_ddr_clk_export : out std_logic; -- export
ram_diag_bg_ddr_reset_export : out std_logic; -- export
reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
reg_diag_rx_seq_ddr_reset_export : out std_logic; -- export
reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
...@@ -347,9 +283,78 @@ PACKAGE qsys_unb1_test_pkg IS ...@@ -347,9 +283,78 @@ PACKAGE qsys_unb1_test_pkg IS
reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
reg_diag_tx_seq_10gbe_reset_export : out std_logic -- export reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
reg_io_ddr_mb_i_reset_export : out std_logic; -- export
reg_io_ddr_mb_i_clk_export : out std_logic; -- export
reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
reg_io_ddr_mb_i_write_export : out std_logic; -- export
reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_io_ddr_mb_i_read_export : out std_logic; -- export
reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
reg_io_ddr_mb_ii_write_export : out std_logic; -- export
reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_io_ddr_mb_ii_read_export : out std_logic; -- export
reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
); );
end component qsys_unb1_test; end component qsys_unb1_test;
END qsys_unb1_test_pkg; END qsys_unb1_test_pkg;
boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+ 499
− 327
View file @ e5d3bcf4
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