From e5d3bcf433aaab96794097ec7856d1fea0e40840 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Fri, 14 Aug 2015 14:32:26 +0000
Subject: [PATCH] Added new ddr versions
---
.../designs/unb1_test/src/vhdl/ddr_stream.vhd | 427 +++------
.../unb1_test/src/vhdl/mmm_unb1_test.vhd | 517 ++++++-----
.../unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd | 137 +--
.../designs/unb1_test/src/vhdl/unb1_test.vhd | 826 +++++++++++-------
4 files changed, 956 insertions(+), 951 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
index 94c979b48f..7d51b6de51 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
@@ -1,8 +1,7 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
@@ -20,331 +19,171 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, diag_lib, io_ddr_lib, reorder_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE common_lib.common_interface_layers_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
-USE reorder_lib.reorder_pkg.ALL;
-USE work.unb1_test_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddr_stream IS
GENERIC (
- g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_stratixiv;
- g_nof_streams : NATURAL;
- g_data_w : NATURAL;
-
- g_bg_block_size : NATURAL := 1024;
- g_bg_gapsize : NATURAL := 0;
- g_bg_blocks_per_sync : NATURAL := 200000;
-
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
- g_ena_pre_transp : BOOLEAN := FALSE;
- g_reorder_seq : t_reorder_seq := c_reorder_seq_same
+ g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_select_default;
+ g_tech_ddr : t_c_tech_ddr;
+ g_st_dat_w : NATURAL := 64 -- Any power of two 8..256
);
PORT (
-- System
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
-
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
-
- -- blockgen mm
- reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
- reg_diag_bg_miso : OUT t_mem_miso;
- ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
- ram_diag_bg_miso : OUT t_mem_miso;
- reg_diag_tx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_diag_tx_seq_miso : OUT t_mem_miso;
-
- -- bsn
- reg_bsn_monitor_mosi : IN t_mem_mosi;
- reg_bsn_monitor_miso : OUT t_mem_miso;
-
- -- databuffer
- reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_diag_data_buf_miso : OUT t_mem_miso;
- ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_diag_data_buf_miso : OUT t_mem_miso;
- reg_diag_rx_seq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_diag_rx_seq_miso : OUT t_mem_miso;
-
- -- IO DDR register map
- reg_io_ddr_mosi : IN t_mem_mosi;
- reg_io_ddr_miso : OUT t_mem_miso;
-
- -- Reorder transpose
- ram_ss_ss_transp_mosi : IN t_mem_mosi;
- ram_ss_ss_transp_miso : OUT t_mem_miso;
-
- -- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr3_phy_in;
- MB_I_IO : INOUT t_tech_ddr3_phy_io;
- MB_I_OU : OUT t_tech_ddr3_phy_ou
- );
-END ddr_stream;
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ ddr_ref_clk : IN STD_LOGIC;
+ ddr_ref_rst : IN STD_LOGIC;
-ARCHITECTURE str OF ddr_stream IS
+ -- Clock outputs
+ ddr_out_clk : OUT STD_LOGIC;
+ ddr_out_rst : OUT STD_LOGIC;
- -- Block generator
- CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ -- MM interface
+ reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_io_ddr_miso : OUT t_mem_miso;
- CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size;
- CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi : IN t_mem_mosi;
+ reg_diag_data_buf_miso : OUT t_mem_miso;
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi : IN t_mem_mosi;
+ ram_diag_data_buf_miso : OUT t_mem_miso;
- -- ddr
- CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
- CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi : IN t_mem_mosi;
+ reg_diag_tx_seq_miso : OUT t_mem_miso;
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi : IN t_mem_mosi;
+ reg_diag_rx_seq_miso : OUT t_mem_miso;
- SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
- SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- -- Signals to interface with the DDR conroller and memory model.
- SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
- SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
-
- SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL to_mem_sosi : t_dp_sosi;
-
- SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL from_mem_sosi : t_dp_sosi;
-
- SIGNAL ddr_ref_rst : STD_LOGIC;
- SIGNAL ddr_out_clk_i : STD_LOGIC;
- SIGNAL ddr_out_rst_i : STD_LOGIC;
-
-BEGIN
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
+ term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
- -----------------------------------------------------------------------------
- -- TX: Block generator and DP fifo
- -----------------------------------------------------------------------------
- u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
- GENERIC MAP (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & NATURAL'IMAGE(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => TRUE
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => '1',
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
+ -- SO-DIMM Memory Bank I = ddr3_I
+ phy_3_in : IN t_tech_ddr3_phy_in;
+ phy_3_io : INOUT t_tech_ddr3_phy_io;
+ phy_3_ou : OUT t_tech_ddr3_phy_ou
);
+END ddr_stream;
+ARCHITECTURE str OF ddr_stream IS
- u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
- GENERIC MAP (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => TRUE,
- --g_sync_timeout => g_bg_blocks_per_sync*(g_bg_block_size+g_bg_gapsize),
- g_cnt_sop_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync+1),
- g_cnt_valid_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync*g_bg_block_size+1),
- g_log_first_bsn => TRUE
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
-
- diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
-
- u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
- GENERIC MAP (
- g_nof_streams => g_nof_streams,
- g_data_w => 32, --g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => FALSE, -- sync by reading last address of data buffer
- g_use_rx_seq => TRUE
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
-
-
- u_transpose: ENTITY reorder_lib.reorder_transpose
- GENERIC MAP(
- g_nof_streams => g_nof_streams,
- g_in_dat_w => g_data_w,
- g_frame_size_in => g_reorder_seq.wr_chunksize,
- g_frame_size_out => g_reorder_seq.wr_chunksize,
- g_use_complex => FALSE,
- g_ena_pre_transp => g_ena_pre_transp,
- g_reorder_seq => g_reorder_seq
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
-
- -- ST sink
- snk_out_arr => block_gen_src_in_arr,
- snk_in_arr => block_gen_src_out_arr,
-
- -- ST source
- src_in_arr => (OTHERS => c_dp_siso_rdy),
- src_out_arr => diag_data_buf_snk_in_arr,
+ CONSTANT c_wr_data_w : NATURAL := g_st_dat_w;
+ CONSTANT c_rd_data_w : NATURAL := g_st_dat_w;
+ CONSTANT c_data_w : NATURAL := g_st_dat_w;
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+ CONSTANT c_wr_fifo_depth : NATURAL := 1024; -- >=16 , defined at DDR side of the FIFO.
+ CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- -- Control interface to the external memory
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
+ CONSTANT c_use_bg : BOOLEAN := FALSE;
+ CONSTANT c_use_tx_seq : BOOLEAN := TRUE;
+ CONSTANT c_use_db : BOOLEAN := FALSE;
+ CONSTANT c_use_rx_seq : BOOLEAN := TRUE;
+ CONSTANT c_buf_nof_data : NATURAL := 1024;
+ CONSTANT c_nof_streams : NATURAL := 1;
+ CONSTANT c_seq_dat_w : NATURAL := 16;
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
+ SIGNAL en_sync : STD_LOGIC;
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
+ SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- Output SOSI that contains the waveform data
+ SIGNAL in_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- );
+BEGIN
- u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
- GENERIC MAP(
- g_rst_level => '1',
- g_delay_len => 40
- )
- PORT MAP(
- clk => dp_clk,
- in_rst => '0',
- out_rst => ddr_ref_rst
- );
+ u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
+ GENERIC MAP(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => g_st_dat_w,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => g_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ PORT MAP(
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk,
+ ctlr_rst_out => ddr_out_rst,
+
+ ctlr_clk_in => dp_clk,
+ ctlr_rst_in => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => term_ctrl_out,
+ term_ctrl_in => term_ctrl_in,
+
+ -- DDR3 PHY external interface
+ phy3_in => phy_3_in,
+ phy3_io => phy_3_io,
+ phy3_ou => phy_3_ou,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso
+ );
- ------------------------------------------------------------------------------
- -- DDR3 MODULE 0, MB_I
- ------------------------------------------------------------------------------
- u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
- GENERIC MAP(
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => FALSE,
- g_wr_data_w => g_data_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => g_data_w,
- g_wr_flush_mode => "SYN",
- g_wr_flush_use_channel => FALSE,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM register map for DDR controller status info
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- DDR reference clock
- ctlr_ref_clk => dp_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk_i,
- ctlr_rst_out => ddr_out_rst_i,
-
- ctlr_clk_in => ddr_out_clk_i,
- ctlr_rst_in => ddr_out_rst_i,
-
-
- -- Driver clock domain
- dvr_clk => ddr_out_clk_i,
- dvr_rst => ddr_out_rst_i,
-
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Write FIFO clock domain
- wr_clk => ddr_out_clk_i,
- wr_rst => ddr_out_rst_i,
-
- wr_fifo_usedw => OPEN,
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- -- Read FIFO clock domain
- rd_clk => ddr_out_clk_i,
- rd_rst => ddr_out_rst_i,
-
- rd_fifo_usedw => OPEN,
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU
- );
END str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 47e798d226..91c8309633 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -53,80 +53,73 @@ ENTITY mmm_unb1_test IS
g_bg_block_size : NATURAL
);
PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
- pout_wdi : OUT STD_LOGIC;
-
-- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
-
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
-- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
-
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
-- UniBoard I2C sensors
- reg_unb_sens_mosi : OUT t_mem_mosi;
- reg_unb_sens_miso : IN t_mem_miso;
-
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
-- PPSH
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso;
-
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+
-- eth1g
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
- eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
-- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
+ reg_dpmm_data_mosi : OUT t_mem_mosi;
+ reg_dpmm_data_miso : IN t_mem_miso;
+ reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
+ reg_dpmm_ctrl_miso : IN t_mem_miso;
-- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
+ reg_mmdp_data_mosi : OUT t_mem_mosi;
+ reg_mmdp_data_miso : IN t_mem_miso;
+ reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
+ reg_mmdp_ctrl_miso : IN t_mem_miso;
-- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso;
-- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso;
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso;
-- block gen
- ram_diag_bg_1GbE_mosi : OUT t_mem_mosi;
- ram_diag_bg_1GbE_miso : IN t_mem_miso;
- reg_diag_bg_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_bg_1GbE_miso : IN t_mem_miso;
- reg_diag_tx_seq_1GbE_mosi : OUT t_mem_mosi;
- reg_diag_tx_seq_1GbE_miso : IN t_mem_miso;
-
- ram_diag_bg_10GbE_mosi : OUT t_mem_mosi;
- ram_diag_bg_10GbE_miso : IN t_mem_miso;
- reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
- reg_diag_bg_10GbE_miso : IN t_mem_miso;
- reg_diag_tx_seq_10GbE_mosi : OUT t_mem_mosi;
- reg_diag_tx_seq_10GbE_miso : IN t_mem_miso;
-
- ram_diag_bg_ddr_mosi : OUT t_mem_mosi;
- ram_diag_bg_ddr_miso : IN t_mem_miso;
- reg_diag_bg_ddr_mosi : OUT t_mem_mosi;
- reg_diag_bg_ddr_miso : IN t_mem_miso;
- reg_diag_tx_seq_ddr_mosi : OUT t_mem_mosi;
- reg_diag_tx_seq_ddr_miso : IN t_mem_miso;
+ ram_diag_bg_1GbE_mosi : OUT t_mem_mosi;
+ ram_diag_bg_1GbE_miso : IN t_mem_miso;
+ reg_diag_bg_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_bg_1GbE_miso : IN t_mem_miso;
+ reg_diag_tx_seq_1GbE_mosi : OUT t_mem_mosi;
+ reg_diag_tx_seq_1GbE_miso : IN t_mem_miso;
+
+ ram_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ ram_diag_bg_10GbE_miso : IN t_mem_miso;
+ reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_bg_10GbE_miso : IN t_mem_miso;
+ reg_diag_tx_seq_10GbE_mosi : OUT t_mem_mosi;
+ reg_diag_tx_seq_10GbE_miso : IN t_mem_miso;
-- dp_offload_tx
reg_dp_offload_tx_1GbE_mosi : OUT t_mem_mosi;
@@ -150,8 +143,6 @@ ENTITY mmm_unb1_test IS
reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
reg_bsn_monitor_10GbE_mosi : OUT t_mem_mosi;
reg_bsn_monitor_10GbE_miso : IN t_mem_miso;
- reg_bsn_monitor_ddr_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_ddr_miso : IN t_mem_miso;
-- databuffer
ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
@@ -160,7 +151,7 @@ ENTITY mmm_unb1_test IS
reg_diag_data_buf_1GbE_miso : IN t_mem_miso;
reg_diag_rx_seq_1GbE_mosi : OUT t_mem_mosi;
reg_diag_rx_seq_1GbE_miso : IN t_mem_miso;
-
+
ram_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
ram_diag_data_buf_10GbE_miso : IN t_mem_miso;
reg_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
@@ -168,24 +159,41 @@ ENTITY mmm_unb1_test IS
reg_diag_rx_seq_10GbE_mosi : OUT t_mem_mosi;
reg_diag_rx_seq_10GbE_miso : IN t_mem_miso;
- ram_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_ddr_miso : IN t_mem_miso;
- reg_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_ddr_miso : IN t_mem_miso;
- reg_diag_rx_seq_ddr_mosi : OUT t_mem_mosi;
- reg_diag_rx_seq_ddr_miso : IN t_mem_miso;
-
-- tr_10GbE
- reg_tr_10GbE_mosi : OUT t_mem_mosi;
- reg_tr_10GbE_miso : IN t_mem_miso;
- reg_tr_xaui_mosi : OUT t_mem_mosi;
- reg_tr_xaui_miso : IN t_mem_miso;
+ reg_tr_10GbE_mosi : OUT t_mem_mosi;
+ reg_tr_10GbE_miso : IN t_mem_miso;
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso;
+
+ -- DDR3 : MB I
+ reg_io_ddr_MB_I_mosi : OUT t_mem_mosi;
+ reg_io_ddr_MB_I_miso : IN t_mem_miso;
+
+ reg_diag_tx_seq_ddr_MB_I_mosi : OUT t_mem_mosi;
+ reg_diag_tx_seq_ddr_MB_I_miso : IN t_mem_miso;
+
+ reg_diag_rx_seq_ddr_MB_I_mosi : OUT t_mem_mosi;
+ reg_diag_rx_seq_ddr_MB_I_miso : IN t_mem_miso;
+
+ reg_diag_data_buf_ddr_MB_I_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_ddr_MB_I_miso : IN t_mem_miso;
+ ram_diag_data_buf_ddr_MB_I_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_ddr_MB_I_miso : IN t_mem_miso;
- ram_ss_ss_transp_mosi : OUT t_mem_mosi;
- ram_ss_ss_transp_miso : IN t_mem_miso;
+ -- DDR3 : MB II
+ reg_io_ddr_MB_II_mosi : OUT t_mem_mosi;
+ reg_io_ddr_MB_II_miso : IN t_mem_miso;
- reg_io_ddr_mosi : OUT t_mem_mosi;
- reg_io_ddr_miso : IN t_mem_miso
+ reg_diag_tx_seq_ddr_MB_II_mosi : OUT t_mem_mosi;
+ reg_diag_tx_seq_ddr_MB_II_miso : IN t_mem_miso;
+
+ reg_diag_rx_seq_ddr_MB_II_mosi : OUT t_mem_mosi;
+ reg_diag_rx_seq_ddr_MB_II_miso : IN t_mem_miso;
+
+ reg_diag_data_buf_ddr_MB_II_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_ddr_MB_II_miso : IN t_mem_miso;
+ ram_diag_data_buf_ddr_MB_II_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_ddr_MB_II_miso : IN t_mem_miso
);
END mmm_unb1_test;
@@ -194,7 +202,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
-- Block generator
CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
- CONSTANT c_ram_diag_bg_ddr_addr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_databuffer_ddr_addr_w : NATURAL := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
@@ -217,46 +225,36 @@ ARCHITECTURE str OF mmm_unb1_test IS
CONSTANT c_reg_dp_offload_rx_10GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_10GbE_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_10GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_dp_offload_rx_10GbE_hdr_dat_adr_w));
- -- reorder
- -- v--- FIXME: g_frame_size_in
- CONSTANT c_ram_ss_ss_transp_adr_w : NATURAL := ceil_log2(256 * c_reorder_seq_same.rd_chunksize); -- 14
-
-- tr_10GbE
- CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
- CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_10GbE_adr_w));
+ CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
+ CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_10GbE_adr_w));
-- tr_xaui
- CONSTANT c_reg_tr_xaui_adr_w : NATURAL := 9;
- CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w));
+ CONSTANT c_reg_tr_xaui_adr_w : NATURAL := 9;
+ CONSTANT c_reg_tr_xaui_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_reg_tr_xaui_adr_w));
-- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
- CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
- CONSTANT c_reg_rsp_bsn_monitor_ddr_adr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-
- CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
- CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
+ CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
+ CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
-- Simulation
- CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
- CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
-
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+ CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+ CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
- CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+ SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
+ SIGNAL sim_eth_psc_access : STD_LOGIC;
+ SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_reg_miso : t_mem_miso;
+ SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
- SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
- SIGNAL sim_eth_psc_access : STD_LOGIC;
- SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_reg_miso : t_mem_miso;
- SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_reset_n : STD_LOGIC;
- SIGNAL i_reset_n : STD_LOGIC;
-
-
-
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
@@ -270,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
+ mm_master_in : IN t_mem_miso
);
END COMPONENT;
@@ -283,46 +281,39 @@ BEGIN
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
-
- u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
- u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
- u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
- u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
- u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
- u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+ u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
- u_mm_file_reg_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_bg_ddr_mosi, reg_diag_bg_ddr_miso);
- u_mm_file_ram_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DDR")
- PORT MAP(mm_rst, mm_clk, ram_diag_bg_ddr_mosi, ram_diag_bg_ddr_miso);
- u_mm_file_reg_diag_tx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_mosi, reg_diag_tx_seq_ddr_miso);
+ u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+ u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
- u_mm_file_reg_dp_offload_tx_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
+ u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ u_mm_file_reg_dp_offload_tx_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
@@ -338,9 +329,6 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
- u_mm_file_reg_bsn_monitor_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_DDR")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_ddr_mosi, reg_bsn_monitor_ddr_miso);
-
u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
@@ -356,28 +344,36 @@ BEGIN
u_mm_file_reg_diag_rx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
- u_mm_file_reg_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_mosi, reg_diag_data_buf_ddr_miso);
- u_mm_file_ram_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_mosi, ram_diag_data_buf_ddr_miso);
- u_mm_file_reg_diag_rx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR")
- PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_mosi, reg_diag_rx_seq_ddr_miso);
-
- u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
-
- u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
-
- -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
-
- u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")--, c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
-
- u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")--, c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
+ u_mm_file_reg_io_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
+
+ u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")--, c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
+
+ u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")--, c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
@@ -420,7 +416,7 @@ BEGIN
----------------------------------------------------------------------------
- -- QSYS
+ -- QSYS
----------------------------------------------------------------------------
i_reset_n <= NOT mm_rst;
@@ -428,9 +424,9 @@ BEGIN
u_qsys : qsys_unb1_test
PORT MAP (
- clk_0 => mm_clk,
+ clk_0 => mm_clk,
reset_n => i_reset_n,
-
+
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
@@ -451,7 +447,7 @@ BEGIN
coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-
+
-- the_reg_unb_sens
coe_clk_export_from_the_reg_unb_sens => OPEN,
coe_reset_export_from_the_reg_unb_sens => OPEN,
@@ -460,7 +456,7 @@ BEGIN
coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
+
-- the_reg_dpmm_data
coe_clk_export_from_the_reg_dpmm_data => OPEN,
coe_reset_export_from_the_reg_dpmm_data => OPEN,
@@ -523,38 +519,38 @@ BEGIN
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
+
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
+
-- the_rom_system_info
coe_clk_export_from_the_rom_system_info => OPEN,
coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
+
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
out_port_from_the_pio_wdi => pout_wdi,
-
+
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 DOWNTO 0),
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0 DOWNTO 0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_tr_10GbE
+ -- the_reg_tr_10GbE
coe_clk_export_from_the_reg_tr_10GbE => OPEN,
coe_reset_export_from_the_reg_tr_10GbE => OPEN,
coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
@@ -564,7 +560,7 @@ BEGIN
coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_tr_xaui
+ -- the_reg_tr_xaui
coe_clk_export_from_the_reg_tr_xaui => OPEN,
coe_reset_export_from_the_reg_tr_xaui => OPEN,
coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_multi_adr_w-1 DOWNTO 0),
@@ -607,23 +603,6 @@ BEGIN
ram_diag_bg_10GbE_reset_export => OPEN,
ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_diag_bg_ddr
- reg_diag_bg_ddr_address_export => reg_diag_bg_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- reg_diag_bg_ddr_clk_export => OPEN,
- reg_diag_bg_ddr_read_export => reg_diag_bg_ddr_mosi.rd,
- reg_diag_bg_ddr_readdata_export => reg_diag_bg_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_bg_ddr_reset_export => OPEN,
- reg_diag_bg_ddr_write_export => reg_diag_bg_ddr_mosi.wr,
- reg_diag_bg_ddr_writedata_export => reg_diag_bg_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_ram_diag_bg_ddr
- ram_diag_bg_ddr_address_export => ram_diag_bg_ddr_mosi.address(c_ram_diag_bg_ddr_addr_w-1 DOWNTO 0),
- ram_diag_bg_ddr_clk_export => OPEN,
- ram_diag_bg_ddr_read_export => ram_diag_bg_ddr_mosi.rd,
- ram_diag_bg_ddr_readdata_export => ram_diag_bg_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_ddr_reset_export => OPEN,
- ram_diag_bg_ddr_write_export => ram_diag_bg_ddr_mosi.wr,
- ram_diag_bg_ddr_writedata_export => ram_diag_bg_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_reg_dp_offload_tx_1GbE
reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
@@ -642,7 +621,6 @@ BEGIN
reg_dp_offload_tx_10GbE_write_export => reg_dp_offload_tx_10GbE_mosi.wr,
reg_dp_offload_tx_10GbE_writedata_export => reg_dp_offload_tx_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_reg_dp_offload_tx_1GbE_hdr_dat
reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
@@ -660,8 +638,6 @@ BEGIN
reg_dp_offload_tx_10GbE_hdr_dat_write_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wr,
reg_dp_offload_tx_10GbE_hdr_dat_writedata_export => reg_dp_offload_tx_10GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
-- the_reg_dp_offload_rx_1GbE_hdr_dat
reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
@@ -696,15 +672,6 @@ BEGIN
reg_bsn_monitor_10GbE_reset_export => OPEN,
reg_bsn_monitor_10GbE_write_export => reg_bsn_monitor_10GbE_mosi.wr,
reg_bsn_monitor_10GbE_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_bsn_monitor_ddr
- reg_bsn_monitor_ddr_address_export => reg_bsn_monitor_ddr_mosi.address(c_reg_rsp_bsn_monitor_ddr_adr_w-1 DOWNTO 0),
- reg_bsn_monitor_ddr_clk_export => OPEN,
- reg_bsn_monitor_ddr_read_export => reg_bsn_monitor_ddr_mosi.rd,
- reg_bsn_monitor_ddr_readdata_export => reg_bsn_monitor_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_ddr_reset_export => OPEN,
- reg_bsn_monitor_ddr_write_export => reg_bsn_monitor_ddr_mosi.wr,
- reg_bsn_monitor_ddr_writedata_export => reg_bsn_monitor_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_ram_diag_data_buffer_1GbE
ram_diag_data_buffer_1GbE_address_export => ram_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
@@ -722,15 +689,6 @@ BEGIN
ram_diag_data_buffer_10GbE_reset_export => OPEN,
ram_diag_data_buffer_10GbE_write_export => ram_diag_data_buf_10GbE_mosi.wr,
ram_diag_data_buffer_10GbE_writedata_export => ram_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_ram_diag_data_buffer_ddr
- ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
- ram_diag_data_buffer_ddr_clk_export => OPEN,
- ram_diag_data_buffer_ddr_read_export => ram_diag_data_buf_ddr_mosi.rd,
- ram_diag_data_buffer_ddr_readdata_export => ram_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_ddr_reset_export => OPEN,
- ram_diag_data_buffer_ddr_write_export => ram_diag_data_buf_ddr_mosi.wr,
- ram_diag_data_buffer_ddr_writedata_export => ram_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_reg_diag_data_buffer_1GbE
reg_diag_data_buffer_1GbE_address_export => reg_diag_data_buf_1GbE_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
@@ -748,15 +706,6 @@ BEGIN
reg_diag_data_buffer_10GbE_reset_export => OPEN,
reg_diag_data_buffer_10GbE_write_export => reg_diag_data_buf_10GbE_mosi.wr,
reg_diag_data_buffer_10GbE_writedata_export => reg_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
- -- the_reg_diag_data_buffer_ddr
- reg_diag_data_buffer_ddr_address_export => reg_diag_data_buf_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
- reg_diag_data_buffer_ddr_clk_export => OPEN,
- reg_diag_data_buffer_ddr_read_export => reg_diag_data_buf_ddr_mosi.rd,
- reg_diag_data_buffer_ddr_readdata_export => reg_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_ddr_reset_export => OPEN,
- reg_diag_data_buffer_ddr_write_export => reg_diag_data_buf_ddr_mosi.wr,
- reg_diag_data_buffer_ddr_writedata_export => reg_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- reg_diag_tx_seq_10GbE
reg_diag_tx_seq_10GbE_address_export => reg_diag_tx_seq_10GbE_mosi.address(4-1 DOWNTO 0),
@@ -794,45 +743,85 @@ BEGIN
reg_diag_rx_seq_1GbE_reset_export => OPEN,
reg_diag_rx_seq_1GbE_write_export => reg_diag_rx_seq_1GbE_mosi.wr,
reg_diag_rx_seq_1GbE_writedata_export => reg_diag_rx_seq_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- -- reg_diag_tx_seq_ddr
- reg_diag_tx_seq_ddr_address_export => reg_diag_tx_seq_ddr_mosi.address(2-1 DOWNTO 0),
- reg_diag_tx_seq_ddr_clk_export => OPEN,
- reg_diag_tx_seq_ddr_read_export => reg_diag_tx_seq_ddr_mosi.rd,
- reg_diag_tx_seq_ddr_readdata_export => reg_diag_tx_seq_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_tx_seq_ddr_reset_export => OPEN,
- reg_diag_tx_seq_ddr_write_export => reg_diag_tx_seq_ddr_mosi.wr,
- reg_diag_tx_seq_ddr_writedata_export => reg_diag_tx_seq_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- reg_diag_rx_seq_ddr
- reg_diag_rx_seq_ddr_address_export => reg_diag_rx_seq_ddr_mosi.address(3-1 DOWNTO 0),
- reg_diag_rx_seq_ddr_clk_export => OPEN,
- reg_diag_rx_seq_ddr_read_export => reg_diag_rx_seq_ddr_mosi.rd,
- reg_diag_rx_seq_ddr_readdata_export => reg_diag_rx_seq_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_diag_rx_seq_ddr_reset_export => OPEN,
- reg_diag_rx_seq_ddr_write_export => reg_diag_rx_seq_ddr_mosi.wr,
- reg_diag_rx_seq_ddr_writedata_export => reg_diag_rx_seq_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
-
- -- ram_ss_ss_wide
- ram_ss_ss_wide_address_export => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
- ram_ss_ss_wide_clk_export => OPEN,
- ram_ss_ss_wide_read_export => ram_ss_ss_transp_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_write_export => ram_ss_ss_transp_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- reg_io_ddr
- reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 DOWNTO 0),
- reg_io_ddr_clk_export => OPEN,
- reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
- reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_io_ddr_reset_export => OPEN,
- reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
- reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
+ reg_io_ddr_MB_I_clk_export => OPEN,
+ reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
+ reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_io_ddr_MB_I_reset_export => OPEN,
+ reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
+ reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
+ reg_io_ddr_MB_II_clk_export => OPEN,
+ reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
+ reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_io_ddr_MB_II_reset_export => OPEN,
+ reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
+ reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w-1 downto 0),
+
+ reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 downto 0),
+ reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w-1 downto 0),
+
+ reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
+ reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
+ reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
+ ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index eb56afedc7..2b89f7c9ce 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -28,7 +28,6 @@ PACKAGE qsys_unb1_test_pkg IS
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
component qsys_unb1_test is
-
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
@@ -152,20 +151,6 @@ PACKAGE qsys_unb1_test_pkg IS
reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_reset_export : out std_logic; -- export
reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
@@ -271,55 +256,6 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_ddr_read_export : out std_logic; -- export
- reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_ddr_write_export : out std_logic; -- export
- reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
- reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
- reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ddr_read_export : out std_logic; -- export
- reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ddr_write_export : out std_logic; -- export
- reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ddr_clk_export : out std_logic; -- export
- reg_diag_bg_ddr_reset_export : out std_logic; -- export
- ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ddr_read_export : out std_logic; -- export
- ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ddr_write_export : out std_logic; -- export
- ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ddr_clk_export : out std_logic; -- export
- ram_diag_bg_ddr_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
@@ -347,9 +283,78 @@ PACKAGE qsys_unb1_test_pkg IS
reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
-
end component qsys_unb1_test;
END qsys_unb1_test_pkg;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 189af6ce28..4ee6629e28 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -62,11 +62,11 @@ ENTITY unb1_test IS
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-
+
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
-
+
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
@@ -103,12 +103,12 @@ ENTITY unb1_test IS
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
- MB_I_OU : OUT t_tech_ddr3_phy_ou
+ MB_I_OU : OUT t_tech_ddr3_phy_ou;
- -- SO-DIMM Memory Bank II
- -- MB_II_IN : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
- -- MB_II_IO : INOUT t_tech_ddr3_phy_io;
- -- MB_II_OU : OUT t_tech_ddr3_phy_ou
+ -- SO-DIMM Memory Bank II
+ MB_II_IN : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ MB_II_IO : INOUT t_tech_ddr3_phy_io;
+ MB_II_OU : OUT t_tech_ddr3_phy_ou
);
END unb1_test;
@@ -117,15 +117,17 @@ END unb1_test;
ARCHITECTURE str OF unb1_test IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 2);
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 2);
- CONSTANT c_use_front : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
- CONSTANT c_use_back : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
+ CONSTANT c_use_front : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_back : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
-- Revision controlled constants
- CONSTANT c_use_1GbE : BOOLEAN := g_design_name="unb1_test_1GbE" OR g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
- CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
- CONSTANT c_use_ddr : BOOLEAN := g_design_name="unb1_test_ddr" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_1GbE : BOOLEAN := g_design_name="unb1_test_1GbE" OR g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_ddr_MB_I : BOOLEAN := g_design_name="unb1_test_ddr_MB_I";
+ CONSTANT c_use_ddr_MB_II : BOOLEAN := g_design_name="unb1_test_ddr_MB_II";
+ CONSTANT c_use_ddr_MB_I_II : BOOLEAN := g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
-- max useful peripherals (FIXME read these constants from board lib)
@@ -133,154 +135,155 @@ ARCHITECTURE str OF unb1_test IS
-- ddr
- CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- CONSTANT c_use_MB_I : NATURAL := sel_a_b(c_use_ddr,1,0); -- 1: use MB_I 0: do not use
- CONSTANT c_use_MB_II : NATURAL := 0;
-
- CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_use_1GbE, 1, 0),
- sel_a_b(c_use_front,1, 0),
- 0,
- sel_a_b(c_use_back, 1, 0),
- sel_a_b(c_use_MB_I, 1, 0),
- sel_a_b(c_use_MB_II,1, 0),
- 0, 1);
-
- CONSTANT c_nof_streams_10GbE : NATURAL := sel_a_b(c_use_10GbE,3,0);
- CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0);
- CONSTANT c_nof_streams_ddr : NATURAL := sel_a_b(c_use_MB_I,sel_a_b(c_use_MB_II,2,1),0);
- CONSTANT c_nof_streams : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
- CONSTANT c_nof_streams_eth : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE;
- CONSTANT c_data_w_32 : NATURAL := c_eth_data_w; -- 1GbE
- CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
+ CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
+ CONSTANT c_use_MB_I : NATURAL := sel_a_b((c_use_ddr_MB_I OR c_use_ddr_MB_I_II),1,0); -- 1: use MB_I 0: do not use
+ CONSTANT c_use_MB_II : NATURAL := sel_a_b((c_use_ddr_MB_II OR c_use_ddr_MB_I_II),1,0); -- 1: use MB_II 0: do not use
+
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_use_1GbE, 1, 0),
+ sel_a_b(c_use_front,1, 0),
+ 0,
+ sel_a_b(c_use_back, 1, 0),
+ sel_a_b(c_use_MB_I, 1, 0),
+ sel_a_b(c_use_MB_II,1, 0),
+ 0, 1);
+
+ CONSTANT c_nof_streams_10GbE : NATURAL := sel_a_b(c_use_10GbE,3,0);
+ CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0);
+ CONSTANT c_nof_streams_ddr : NATURAL := sel_a_b(c_use_MB_I,sel_a_b(c_use_MB_II,2,1),0);
+ CONSTANT c_nof_streams : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE + c_nof_streams_ddr;
+ CONSTANT c_nof_streams_eth : NATURAL := c_nof_streams_1GbE + c_nof_streams_10GbE;
+ CONSTANT c_data_w_32 : NATURAL := c_eth_data_w; -- 1GbE
+ CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
-- ddr
- CONSTANT c_ddr_master : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
- CONSTANT c_ddr_slave : t_c_tech_ddr := c_tech_ddr3_4g_800m_slave;
+ CONSTANT c_ddr_master : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
+ CONSTANT c_ddr_slave : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_slave;
-- Block generator constants
- CONSTANT c_bg_block_size : NATURAL := 900;
- CONSTANT c_bg_gapsize : NATURAL := 100;
- CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ CONSTANT c_bg_block_size : NATURAL := 900;
+ CONSTANT c_bg_gapsize : NATURAL := 100;
+ CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
- CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
- CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+ CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
+ CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
+ CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
- CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
- CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
- CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
+ CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
+ CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
+ CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
- CONSTANT c_max_udp_payload_nof_words_1GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_32;
- CONSTANT c_max_udp_payload_nof_words_10GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_64;
- CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_max_nof_blocks_per_packet_1GbE : NATURAL := c_max_udp_payload_nof_words_1GbE/c_min_nof_words_per_block;
- CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
+ CONSTANT c_max_udp_payload_nof_words_1GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_32;
+ CONSTANT c_max_udp_payload_nof_words_10GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_64;
+ CONSTANT c_min_nof_words_per_block : NATURAL := 1;
+ CONSTANT c_max_nof_blocks_per_packet_1GbE : NATURAL := c_max_udp_payload_nof_words_1GbE/c_min_nof_words_per_block;
+ CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
-- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_clk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
-
- SIGNAL cal_rec_clk : STD_LOGIC;
- SIGNAL epcs_clk : STD_LOGIC;
- SIGNAL sa_rst : STD_LOGIC;
-
- SIGNAL dp_clk : STD_LOGIC;
- SIGNAL dp_rst : STD_LOGIC;
-
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL ddr_ref_rst : STD_LOGIC;
+
+ SIGNAL cal_rec_clk : STD_LOGIC;
+ SIGNAL epcs_clk : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC;
+
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+
-- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
+ SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
-
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
-- eth1g
- SIGNAL eth1g_tse_clk : STD_LOGIC;
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC;
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_data_miso : t_mem_miso;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_data_miso : t_mem_miso;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi;
- SIGNAL reg_epcs_miso : t_mem_miso;
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi;
- SIGNAL reg_remu_miso : t_mem_miso;
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE
- SIGNAL xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL i_xaui_tx_arr : t_xaui_arr(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL i_xaui_rx_arr : t_xaui_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_miso : t_mem_miso;
-
- SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
- SIGNAL reg_tr_xaui_miso : t_mem_miso;
-
- SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
- SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_tx_seq_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_tx_seq_1GbE_miso : t_mem_miso;
-
- SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
- SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_10GbE_miso : t_mem_miso;
- SIGNAL reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_tx_seq_10GbE_miso : t_mem_miso;
-
- SIGNAL reg_diag_bg_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_ddr_miso : t_mem_miso;
- SIGNAL ram_diag_bg_ddr_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_ddr_miso : t_mem_miso;
- SIGNAL reg_diag_tx_seq_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_tx_seq_ddr_miso : t_mem_miso;
+ SIGNAL xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL i_xaui_tx_arr : t_xaui_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL i_xaui_rx_arr : t_xaui_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+
+ SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_1GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_tx_seq_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_1GbE_miso : t_mem_miso;
+
+ SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_diag_tx_seq_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_ddr_MB_I_miso : t_mem_miso;
+
+ SIGNAL reg_diag_tx_seq_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_tx_seq_ddr_MB_II_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
@@ -297,61 +300,80 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_dp_offload_rx_10GbE_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_10GbE_hdr_dat_miso : t_mem_miso;
- SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
- SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
- SIGNAL reg_bsn_monitor_ddr_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_ddr_miso : t_mem_miso;
-
- SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
- SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
-
- SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_10GbE_miso : t_mem_miso;
- SIGNAL reg_diag_rx_seq_10GbE_mosi : t_mem_mosi;
- SIGNAL reg_diag_rx_seq_10GbE_miso : t_mem_miso;
-
- SIGNAL ram_diag_data_buf_ddr_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_ddr_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_ddr_miso : t_mem_miso;
- SIGNAL reg_diag_rx_seq_ddr_mosi : t_mem_mosi;
- SIGNAL reg_diag_rx_seq_ddr_miso : t_mem_miso;
-
- SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL block_gen_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
- SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
-
- SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
- SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
-
- SIGNAL reg_io_ddr_mosi : t_mem_mosi;
- SIGNAL reg_io_ddr_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_10GbE_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_ddr_MB_I_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
+ SIGNAL reg_diag_rx_seq_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_diag_rx_seq_ddr_MB_II_miso : t_mem_miso;
+
+ SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL block_gen_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ SIGNAL reg_io_ddr_MB_I_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_MB_I_miso : t_mem_miso;
+ SIGNAL reg_io_ddr_MB_II_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_MB_II_miso : t_mem_miso;
-- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
+
+ -- DDR3 pass on termination control from master to slave controller
+ SIGNAL term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
+ SIGNAL term_ctrl_in : t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
+
BEGIN
+ u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ PORT MAP(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -361,15 +383,15 @@ BEGIN
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => TRUE,
+ g_dp_clk_use_pll => FALSE,
g_xo_clk_use_pll => TRUE
)
PORT MAP (
@@ -389,14 +411,14 @@ BEGIN
epcs_clk => epcs_clk,
epcs_clk_out => epcs_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => OPEN,
+ dp_clk => OPEN,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
cal_rec_clk => cal_rec_clk,
-
+
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -424,21 +446,21 @@ BEGIN
-- EPCS status/control
reg_epcs_mosi => reg_epcs_mosi,
reg_epcs_miso => reg_epcs_miso,
-
+
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-
+
-- eth1g
eth1g_tse_clk_out => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk,
@@ -450,7 +472,7 @@ BEGIN
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-
+
-- eth1g UDP streaming ports
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
@@ -470,7 +492,7 @@ BEGIN
TESTIO => TESTIO,
-- . I2C Interface to Sensors
SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ SENS_SD => SENS_SD,
-- . 1GbE Control Interface
ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
@@ -493,80 +515,73 @@ BEGIN
g_nof_streams_ddr => 1,--c_nof_streams_ddr,
g_bg_block_size => c_bg_block_size
)
- PORT MAP(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
-- PIOs
- pout_wdi => pout_wdi,
+ pout_wdi => pout_wdi,
-- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
-- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
-- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
-- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
-- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- ram_diag_bg_ddr_mosi => ram_diag_bg_ddr_mosi,
- ram_diag_bg_ddr_miso => ram_diag_bg_ddr_miso,
- reg_diag_bg_ddr_mosi => reg_diag_bg_ddr_mosi,
- reg_diag_bg_ddr_miso => reg_diag_bg_ddr_miso,
- reg_diag_tx_seq_ddr_mosi => reg_diag_tx_seq_ddr_mosi,
- reg_diag_tx_seq_ddr_miso => reg_diag_tx_seq_ddr_miso,
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
@@ -591,8 +606,6 @@ BEGIN
reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
- reg_bsn_monitor_ddr_mosi => reg_bsn_monitor_ddr_mosi,
- reg_bsn_monitor_ddr_miso => reg_bsn_monitor_ddr_miso,
-- databuffer
ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
@@ -609,24 +622,41 @@ BEGIN
reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
- ram_diag_data_buf_ddr_mosi => ram_diag_data_buf_ddr_mosi,
- ram_diag_data_buf_ddr_miso => ram_diag_data_buf_ddr_miso,
- reg_diag_data_buf_ddr_mosi => reg_diag_data_buf_ddr_mosi,
- reg_diag_data_buf_ddr_miso => reg_diag_data_buf_ddr_miso,
- reg_diag_rx_seq_ddr_mosi => reg_diag_rx_seq_ddr_mosi,
- reg_diag_rx_seq_ddr_miso => reg_diag_rx_seq_ddr_miso,
-
-- tr_10GbE
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+ -- DDR3 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR3 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
@@ -646,12 +676,12 @@ BEGIN
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-
+
dp_rst => dp_rst,
dp_clk => dp_clk,
-
+
ID => ID,
-
+
-- blockgen MM
reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
@@ -659,7 +689,7 @@ BEGIN
ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
-
+
-- dp_offload_tx
reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
@@ -667,17 +697,17 @@ BEGIN
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
+
-- dp_offload_rx
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
-
+
-- bsn
reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
-
+
-- databuffer
reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
@@ -705,12 +735,12 @@ BEGIN
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-
+
dp_rst => dp_rst,
dp_clk => dp_clk,
-
+
ID => ID,
-
+
-- blockgen mm
reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
@@ -718,7 +748,7 @@ BEGIN
ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
+
-- dp_offload_tx
reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
@@ -726,17 +756,17 @@ BEGIN
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
+
-- dp_offload_rx
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
+
-- bsn
reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
+
-- databuffer
reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
@@ -773,7 +803,7 @@ BEGIN
clk => SA_CLK,
in_rst => '0',
out_rst => sa_rst
- );
+ );
gen_tr_10GbE : IF c_use_10GbE=TRUE GENERATE
u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
@@ -794,7 +824,7 @@ BEGIN
-- MM interface
mm_rst => mm_rst,
mm_clk => mm_clk,
-
+
reg_mac_mosi => reg_tr_10GbE_mosi,
reg_mac_miso => reg_tr_10GbE_miso,
@@ -807,7 +837,7 @@ BEGIN
src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
-
+
snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
@@ -858,60 +888,202 @@ BEGIN
END GENERATE;
- gen_ddr_stream : IF c_use_ddr = TRUE GENERATE
- u_ddr_stream : ENTITY work.ddr_stream
+ gen_ddr_stream_MB_I : IF c_use_ddr_MB_I = TRUE GENERATE
+ u_ddr_stream_MB_I : ENTITY work.ddr_stream
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
- g_nof_streams => c_nof_streams_ddr,
- g_data_w => c_data_w_32,
- --g_bg_block_size => c_bg_block_size,
- --g_bg_gapsize => c_bg_gapsize,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
g_tech_ddr => c_ddr_master,
- g_reorder_seq => c_reorder_seq_same,
- g_ena_pre_transp => FALSE
+ g_st_dat_w => c_data_w_64
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-
+
dp_rst => dp_rst,
dp_clk => dp_clk,
-
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
-- blockgen mm
- reg_diag_bg_mosi => reg_diag_bg_ddr_mosi,
- reg_diag_bg_miso => reg_diag_bg_ddr_miso,
- ram_diag_bg_mosi => ram_diag_bg_ddr_mosi,
- ram_diag_bg_miso => ram_diag_bg_ddr_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_miso,
-
- -- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_ddr_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_ddr_miso,
-
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_ddr_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_ddr_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_miso,
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Reorder transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_I_IN,
+ phy_3_io => MB_I_IO,
+ phy_3_ou => MB_I_OU
);
END GENERATE;
+
+ gen_ddr_stream_MB_II : IF c_use_ddr_MB_II = TRUE GENERATE
+ u_ddr_stream_MB_II : ENTITY work.ddr_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_tech_ddr => c_ddr_master,
+ g_st_dat_w => c_data_w_64
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
+ -- blockgen mm
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_II_IN,
+ phy_3_io => MB_II_IO,
+ phy_3_ou => MB_II_OU
+ );
+ END GENERATE;
+
+ gen_ddr_dual_stream_MB_I : IF c_use_ddr_MB_I_II = TRUE GENERATE
+ u_ddr_stream_MB_I : ENTITY work.ddr_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_tech_ddr => c_ddr_master,
+ g_st_dat_w => c_data_w_64
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
+ -- blockgen mm
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_I_IN,
+ phy_3_io => MB_I_IO,
+ phy_3_ou => MB_I_OU
+ );
+ END GENERATE;
+
+ gen_ddr_dual_stream_MB_II : IF c_use_ddr_MB_I_II = TRUE GENERATE
+ u_ddr_stream_MB_II : ENTITY work.ddr_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_tech_ddr => c_ddr_master,
+ g_st_dat_w => c_data_w_64
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => OPEN,
+ ddr_out_rst => OPEN,
+
+ -- blockgen mm
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_II_IN,
+ phy_3_io => MB_II_IO,
+ phy_3_ou => MB_II_OU
+ );
+ END GENERATE;
+
+
END str;
--
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