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ddr_stream.vhd 7.32 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddr_stream IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_st_dat_w : NATURAL := 64 -- Any power of two 8..256
);
PORT (
-- System
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
ddr_ref_clk : IN STD_LOGIC;
ddr_ref_rst : IN STD_LOGIC;
-- Clock outputs
ddr_out_clk : OUT STD_LOGIC;
ddr_out_rst : OUT STD_LOGIC;
-- MM interface
reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : OUT t_mem_miso;
-- Data Buffer Control
reg_diag_data_buf_mosi : IN t_mem_mosi;
reg_diag_data_buf_miso : OUT t_mem_miso;
-- Data Buffer Data
ram_diag_data_buf_mosi : IN t_mem_mosi;
ram_diag_data_buf_miso : OUT t_mem_miso;
-- TX Sequencer
reg_diag_tx_seq_mosi : IN t_mem_mosi;
reg_diag_tx_seq_miso : OUT t_mem_miso;
-- RX Sequencer
reg_diag_rx_seq_mosi : IN t_mem_mosi;
reg_diag_rx_seq_miso : OUT t_mem_miso;
-- DDR3 pass on termination control from master to slave controller
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
-- SO-DIMM Memory Bank I = ddr3_I
phy_3_in : IN t_tech_ddr3_phy_in;
phy_3_io : INOUT t_tech_ddr3_phy_io;
phy_3_ou : OUT t_tech_ddr3_phy_ou
);
END ddr_stream;
ARCHITECTURE str OF ddr_stream IS
CONSTANT c_wr_data_w : NATURAL := g_st_dat_w;
CONSTANT c_rd_data_w : NATURAL := g_st_dat_w;
CONSTANT c_data_w : NATURAL := g_st_dat_w;
CONSTANT c_wr_fifo_depth : NATURAL := 1024; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
CONSTANT c_use_bg : BOOLEAN := FALSE;
CONSTANT c_use_tx_seq : BOOLEAN := TRUE;
CONSTANT c_use_db : BOOLEAN := FALSE;
CONSTANT c_use_rx_seq : BOOLEAN := TRUE;
CONSTANT c_buf_nof_data : NATURAL := 1024;
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_seq_dat_w : NATURAL := 16;
SIGNAL en_sync : STD_LOGIC;
SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- Output SOSI that contains the waveform data
SIGNAL in_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
BEGIN
u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP(
-- System
g_technology => g_technology,
g_dp_data_w => g_st_dat_w,
g_dp_seq_dat_w => c_seq_dat_w,
g_dp_wr_fifo_depth => c_wr_fifo_depth,
g_dp_rd_fifo_depth => c_rd_fifo_depth,
-- IO_DDR
g_io_tech_ddr => g_tech_ddr,
-- DIAG data buffer
g_db_use_db => c_use_db,
g_db_buf_nof_data => c_buf_nof_data
)
PORT MAP(
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
---------------------------------------------------------------------------
-- IO_DDR
---------------------------------------------------------------------------
-- DDR reference clock
ctlr_ref_clk => ddr_ref_clk, ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => ddr_out_clk,
ctlr_rst_out => ddr_out_rst,
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- Write / read FIFO status for monitoring purposes (in dp_clk domain)
wr_fifo_usedw => OPEN,
rd_fifo_usedw => OPEN,
-- DDR3 pass on termination control from master to slave controller
term_ctrl_out => term_ctrl_out,
term_ctrl_in => term_ctrl_in,
-- DDR3 PHY external interface
phy3_in => phy_3_in,
phy3_io => phy_3_io,
phy3_ou => phy_3_ou,
---------------------------------------------------------------------------
-- DIAG Tx seq
---------------------------------------------------------------------------
-- MM interface
reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
reg_tx_seq_miso => reg_diag_tx_seq_miso,
---------------------------------------------------------------------------
-- DIAG rx seq with optional data buffer
---------------------------------------------------------------------------
-- MM interface
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
reg_rx_seq_miso => reg_diag_rx_seq_miso
);
END str;