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Eric Kooistra authoredCompile DDR3 memory model from the ip_stratixiv_ddr3_uphy_4g_800_master example design into this library.
Eric Kooistra authoredCompile DDR3 memory model from the ip_stratixiv_ddr3_uphy_4g_800_master example design into this library.
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hdllib.cfg 399 B
hdl_lib_name = ip_stratixiv_ddr3_mem_model
hdl_library_clause_name = ip_stratixiv_ddr3_mem_model_lib
hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
synth_files =
test_bench_files =