diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5a773b59154e28ce4d6f87b4d2788bb3972fa2e5
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Megawizard-generated file msim_setup.tcl.
+
+# Get the memory model fro the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+
+# Assume library work already exists
+
+# Compile the design files in correct order and map them all to library work
+vlog -sv "$IP_DIR/simulation/vhdl/submodules/alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" -work work
+vlog -sv "$IP_DIR/simulation/vhdl/submodules/mentor/alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" -work work
+
+# or use the binary files from the mentor/ subdirectory as in msim_setup.tcl:
+#vlog -sv "$IP_DIR/simulation/vhdl/submodules/alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" -work work
+#vlog -sv "$IP_DIR/simulation/vhdl/submodules/mentor/alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" -work work
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4ce79ca2619b70195495a26e0f09b7c2b87e1b29
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/generate_ip.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate ddr3 memory model using the example design for uniphy IP with MegaWizard
+# Description:
+# No need to create the memory model for other DDR3 sizes, because this memory model fits all ddr3_uphy. It
+# appears that:
+# - the example design for ip_stratixiv_ddr3_uphy_4g_800_slave.v creates the same memory model
+# - the example design for ip_stratixiv_ddr3_uphy_4g_1066_master.v creates the same memory model
+# The memory model files can be compiled by executing compile_ip.tcl in Modelsim.
+# Usage:
+#
+# ./generate_ip.sh
+#
+# Remarks:
+# . This dedicated script is derived from the generic script $UNB/Firmware/software/build/unb_mgw
+#
+
+# Tool settings for selected target "unb1" with stratixiv
+. ${RADIOHDL}/tools/quartus/set_quartus unb1
+
+# The ip_stratixiv_ddr3_uphy_4g_800_master.v IP must have been generated
+
+# Generate memory model using the example design for ip_stratixiv_ddr3_uphy_4g_800_master.v.
+
+cd ../ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation
+quartus_sh -t generate_sim_vhdl_example_design.tcl
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d70ef4e7966fd190cd8cc5ae9413523a4a4f3044
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -0,0 +1,14 @@
+hdl_lib_name = ip_stratixiv_ddr3_mem_model
+hdl_library_clause_name = ip_stratixiv_ddr3_mem_model_lib
+hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+
+synth_files =
+
+test_bench_files =