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Commit ddea43b1 authored by Job van Wee's avatar Job van Wee
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Stage: simulation
Stage: synthesis
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+ 12
− 19
View file @ ddea43b1
...@@ -41,32 +41,31 @@ ENTITY ddrctrl_repack IS ...@@ -41,32 +41,31 @@ ENTITY ddrctrl_repack IS
); );
PORT ( PORT (
clk : IN STD_LOGIC; clk : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
out_of : OUT NATURAL := 0; out_of : OUT NATURAL := 0; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi := c_dp_sosi_init out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
); );
END ddrctrl_repack; END ddrctrl_repack;
ARCHITECTURE rtl OF ddrctrl_repack IS ARCHITECTURE rtl OF ddrctrl_repack IS
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576 CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152 CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
SIGNAL c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
SIGNAL out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
BEGIN BEGIN
-- put the input data into c_v and fill the output vector from c_v
p_clk : PROCESS(clk) p_clk : PROCESS(clk)
VARIABLE a_of : NATURAL := 0; -- amount of overflow VARIABLE a_of : NATURAL := 0; -- amount of overflow
VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0'); -- the vector that stores the input data until the data is put into the output data vector VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0'); -- the vector that stores the input data until the data is put into the output data vector
VARIABLE c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
VARIABLE out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
BEGIN BEGIN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) THEN -- if the input data exceeds the output data vector width IF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) THEN -- if the input data exceeds the output data vector width
IF (out_data_count = 1) THEN -- if the input data exceeds c_v widt IF (out_data_count = 1) THEN -- if the input data exceeds c_v widt
...@@ -76,28 +75,22 @@ BEGIN ...@@ -76,28 +75,22 @@ BEGIN
c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1 out_sosi.valid <= '1'; -- out_sosi.valid 1
c_v_count <= 0; -- reset counter c_v_count := 0; -- reset counter
out_data_count <= 0; -- reset counter out_data_count := 0; -- reset counter
Else -- if the input data exceeds output data vector width but not the c_v vector widt Else -- if the input data exceeds output data vector width but not the c_v vector widt
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1 c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1 out_sosi.valid <= '1'; -- out_sosi.valid 1
out_data_count <= out_data_count + 1; -- increase the counter of out_sosi.data with 1 out_data_count := out_data_count + 1; -- increase the counter of out_sosi.data with 1
END IF; END IF;
ELSE -- if the input data doesn't exceeds the output data vector width ELSE -- if the input data doesn't exceeds the output data vector width
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1 c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.valid <= '0'; -- out_sosi.valid 0 out_sosi.valid <= '0'; -- out_sosi.valid 0
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
END rtl; END rtl;
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+ 34
− 31
View file @ ddea43b1
...@@ -44,11 +44,14 @@ END tb_ddrctrl_repack; ...@@ -44,11 +44,14 @@ END tb_ddrctrl_repack;
ARCHITECTURE tb OF tb_ddrctrl_repack IS ARCHITECTURE tb OF tb_ddrctrl_repack IS
-- constants for running testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock freqency in MHz CONSTANT c_clk_freq : NATURAL := 200; -- clock freqency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock period, 5 ns CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock period, 5 ns
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0); VARIABLE temp : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0);
BEGIN BEGIN
...@@ -57,76 +60,76 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS ...@@ -57,76 +60,76 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
END LOOP; END LOOP;
RETURN temp; RETURN temp;
END FUNCTION c_total_vector_init; END FUNCTION c_total_vector_init;
CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
-- constant for running the test
CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
SIGNAL ctr_of : NATURAL := 0; -- signal which contains the amount of overflow for checking
SIGNAL in_data_cnt : NATURAL := 0;
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell when the testing has started
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
-- input signals for ddrctrl_repack.vhd
SIGNAL clk : STD_LOGIC := '1'; -- clock signal SIGNAL clk : STD_LOGIC := '1'; -- clock signal
SIGNAL in_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- input data signal for ddrctrl_repack SIGNAL in_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- input data signal for ddrctrl_repack
-- output signals from ddrctrl_repack.vhd
SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init; -- output data signal form ddrctrl_repack SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init; -- output data signal form ddrctrl_repack
-- testbench signal
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
-- singals for running the test
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
BEGIN BEGIN
clk <= NOT clk OR tb_end AFTER c_clk_period/2; -- genereting clock signal -- Generating clock
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
p_mm : PROCESS -- Excecuting the test
p_test : PROCESS
BEGIN BEGIN
-- start the test
-- Start the testbench.
tb_end <= '0'; tb_end <= '0';
WAIT UNTIL rising_edge(clk); -- align to rising edge WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
test_running <= '1'; -- start of test test_running <= '1'; -- start of test
-- Filling the input vector g_sim_lengt amount of times. -- filling the input vector g_sim_lengt amount of times
make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
--ASSERT FALSE REPORT "I = " & NATURAL'image(I) SEVERITY NOTE;
in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w); in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
WAIT FOR c_clk_period*1; WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1; in_data_cnt <= in_data_cnt + 1;
END LOOP; END LOOP;
test_running <= '0'; test_running <= '0';
-- Stop the testbench. -- stopping the testbench
WAIT FOR c_clk_period*5; WAIT FOR c_clk_period*5;
tb_end <= '1'; tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
WAIT;
END PROCESS; END PROCESS;
-- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
-- Verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected.
p_verify : PROCESS p_verify : PROCESS
VARIABLE ctr_of : NATURAL := 0; VARIABLE ctr_of : NATURAL := 0;
VARIABLE out_data_cnt : NATURAL := 0; VARIABLE out_data_cnt : NATURAL := 0;
BEGIN BEGIN
WAIT UNTIL out_sosi.valid = '1' AND test_running = '1';
WAIT UNTIL rising_edge(out_sosi.valid); IF out_data_cnt >= 1 THEN
--WAIT FOR c_clk_period*1; IF out_data_cnt mod 2 = 0 THEN
ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
IF test_running = '1' THEN ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
ASSERT FALSE REPORT "ik werk" SEVERITY NOTE;
IF out_data_cnt mod 2 = 1 THEN
ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*(out_data_cnt+1);
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
END IF; END IF;
ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt+1)-1 DOWNTO c_out_data_w*out_data_cnt) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR; ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
out_data_cnt := out_data_cnt + 1;
END IF; END IF;
out_data_cnt := out_data_cnt+1;
END PROCESS; END PROCESS;
-- DUT
u_ddrctrl_repack : ENTITY work.ddrctrl_repack u_ddrctrl_repack : ENTITY work.ddrctrl_repack
GENERIC MAP ( GENERIC MAP (
g_tech_ddr => g_tech_ddr, g_tech_ddr => g_tech_ddr,
......
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