diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
index 3c515a881c4815d0e09dd3716fe0587da3ddc1a6..0011b9c691f8c15aef99ce99ed96cdefc0fbdff6 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
@@ -41,32 +41,31 @@ ENTITY ddrctrl_repack IS
);
PORT (
clk : IN STD_LOGIC;
- in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
- out_of : OUT NATURAL := 0;
- out_sosi : OUT t_dp_sosi := c_dp_sosi_init
+ in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
+ out_of : OUT NATURAL := 0; -- amount of internal overflow this output
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
);
END ddrctrl_repack;
ARCHITECTURE rtl OF ddrctrl_repack IS
+ -- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
- SIGNAL c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
- SIGNAL out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
-
BEGIN
+ -- put the input data into c_v and fill the output vector from c_v
p_clk : PROCESS(clk)
VARIABLE a_of : NATURAL := 0; -- amount of overflow
VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0'); -- the vector that stores the input data until the data is put into the output data vector
+ VARIABLE c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ VARIABLE out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
BEGIN
-
IF rising_edge(clk) THEN
-
IF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) THEN -- if the input data exceeds the output data vector width
IF (out_data_count = 1) THEN -- if the input data exceeds c_v widt
@@ -76,28 +75,22 @@ BEGIN
c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1
- c_v_count <= 0; -- reset counter
- out_data_count <= 0; -- reset counter
+ c_v_count := 0; -- reset counter
+ out_data_count := 0; -- reset counter
Else -- if the input data exceeds output data vector width but not the c_v vector widt
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
- c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1
+ c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1
- out_data_count <= out_data_count + 1; -- increase the counter of out_sosi.data with 1
+ out_data_count := out_data_count + 1; -- increase the counter of out_sosi.data with 1
END IF;
ELSE -- if the input data doesn't exceeds the output data vector width
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
- c_v_count <= c_v_count + 1; -- increase the counter of c_v with 1
+ c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.valid <= '0'; -- out_sosi.valid 0
-
END IF;
-
END IF;
-
END PROCESS;
-
END rtl;
-
-
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
index 3467ce703a6b7705fd8f9371b83d1cfdd888934e..ce51bf4b8e7962e62a759cff782f1e650a9751e7 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
@@ -44,11 +44,14 @@ END tb_ddrctrl_repack;
ARCHITECTURE tb OF tb_ddrctrl_repack IS
+ -- constants for running testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock freqency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock period, 5 ns
- CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
+ -- constant for readability
+ CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
+ -- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0);
BEGIN
@@ -57,76 +60,76 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
- CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
+ -- constant for running the test
+ CONSTANT c_total_vector : STD_LOGIC_VECTOR(g_in_data_w*g_sim_lengt-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
- SIGNAL ctr_of : NATURAL := 0; -- signal which contains the amount of overflow for checking
- SIGNAL in_data_cnt : NATURAL := 0;
-
- SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell when the testing has started
- SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+ -- input signals for ddrctrl_repack.vhd
SIGNAL clk : STD_LOGIC := '1'; -- clock signal
SIGNAL in_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- input data signal for ddrctrl_repack
+ -- output signals from ddrctrl_repack.vhd
SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init; -- output data signal form ddrctrl_repack
+ -- testbench signal
+ SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+
+ -- singals for running the test
+ SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
+ SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
+
BEGIN
- clk <= NOT clk OR tb_end AFTER c_clk_period/2; -- genereting clock signal
+ -- Generating clock
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
- p_mm : PROCESS
+ -- Excecuting the test
+ p_test : PROCESS
BEGIN
-
- -- Start the testbench.
+ -- start the test
tb_end <= '0';
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
test_running <= '1'; -- start of test
- -- Filling the input vector g_sim_lengt amount of times.
+ -- filling the input vector g_sim_lengt amount of times
make_in_data : FOR I IN 0 TO g_sim_lengt-1 LOOP
- --ASSERT FALSE REPORT "I = " & NATURAL'image(I) SEVERITY NOTE;
in_data(g_in_data_w-1 DOWNTO 0) <= TO_UVEC(I, g_in_data_w);
WAIT FOR c_clk_period*1;
in_data_cnt <= in_data_cnt + 1;
END LOOP;
test_running <= '0';
- -- Stop the testbench.
+ -- stopping the testbench
WAIT FOR c_clk_period*5;
tb_end <= '1';
-
- WAIT;
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-
- -- Verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected.
+ -- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
p_verify : PROCESS
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
-
- WAIT UNTIL rising_edge(out_sosi.valid);
- --WAIT FOR c_clk_period*1;
-
- IF test_running = '1' THEN
- ASSERT FALSE REPORT "ik werk" SEVERITY NOTE;
- IF out_data_cnt mod 2 = 1 THEN
- ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*(out_data_cnt+1);
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) SEVERITY ERROR;
+ WAIT UNTIL out_sosi.valid = '1' AND test_running = '1';
+ IF out_data_cnt >= 1 THEN
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
- ASSERT out_sosi.data(c_out_data_w -1 DOWNTO 0) = c_total_vector(c_out_data_w*(out_data_cnt+1)-1 DOWNTO c_out_data_w*out_data_cnt) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
- out_data_cnt := out_data_cnt + 1;
+ ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
+ out_data_cnt := out_data_cnt+1;
END PROCESS;
+ -- DUT
u_ddrctrl_repack : ENTITY work.ddrctrl_repack
GENERIC MAP (
g_tech_ddr => g_tech_ddr,