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Commit dace1a94 authored by Reinier van der Walle's avatar Reinier van der Walle
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added compile_ip.tcl files and edited hdllib.cfg to change the quartus

version number from 151 to 170
parent 70fae082
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hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151 hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
hdl_lib_uses_synth = common hdl_lib_uses_synth = common
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg hdl_lib_technology = ip_arria10_e1sg
...@@ -12,7 +12,7 @@ test_bench_files = ...@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file] [modelsim_project_file]
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file] [quartus_project_file]
......
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_170 ./work/
vmap altera_voltage_sensor_control_170 ./work/
vmap altera_voltage_sensor_sample_store_170 ./work/
vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_170
vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_170
vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_170
vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_170
vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_170
vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_170
vcom "$IP_DIR/../altera_voltage_sensor_170/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_170_hjr63vq.vhd" -work altera_voltage_sensor_170
vcom "$IP_DIR/ip_arria10_e1sg_voltage_sense.vhd" -work ip_arria10_e1sg_voltage_sense
hdl_lib_name = ip_arria10_e1sg_voltage_sense hdl_lib_name = ip_arria10_e1sg_voltage_sense
hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151 hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
hdl_lib_uses_synth = hdl_lib_uses_synth =
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg hdl_lib_technology = ip_arria10_e1sg
......
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