diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..01a94cfcadef81f825a3e671d260e6e99c9ece29
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/clkbuf_global/generated/sim"
+
+vmap altclkctrl_170 ./work/
+vmap ip_arria10_e1sg_clkbuf_global ./work/
+
+
+ vcom "$IP_DIR/../altclkctrl_170/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_170_7fwzyby.vhd" -work altclkctrl_170
+ vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd" -work ip_arria10_e1sg_clkbuf_global
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 14f3f61a13058046e33eb6c53108ea9c2e7aec8e..fec25a7cd5a62ae9fa21b4018f95c428c923aca9 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_clkbuf_global
-hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_151
+hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..88de2e5ff42c9ab93860b9ad6ca388a161525f21
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim"
+
+vmap ip_arria10_e1sg_complex_mult ./work/
+vmap altmult_complex_170 ./work/
+
+
+ vcom "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.vhd" -work altmult_complex_170
+ vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd" -work ip_arria10_e1sg_complex_mult
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..29a31420275d719ea7f559461a8051a2ba3aaf33
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -0,0 +1,41 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddio/generated/sim"
+
+vmap altera_gpio_core20_170 ./work/
+vmap altera_gpio_170 ./work/
+vmap ip_arria10_e1sg_ddio_out_1 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_gpio_core20_170/sim/mentor/altera_gpio.sv" -work altera_gpio_core20_170
+ vcom "$IP_DIR/../altera_gpio_170/sim/ip_arria10_e1sg_ddio_out_1_altera_gpio_170_pqckuoi.vhd" -work altera_gpio_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ddio_out_1.vhd" -work ip_arria10_e1sg_ddio_out_1
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d6dbc8d543a246b60213f36e319fdbfe6abc4ba5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -0,0 +1,95 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+
+vmap altera_merlin_master_translator_170 ./work/
+vmap altera_emif_cal_slave_nf_170 ./work/
+vmap altera_avalon_onchip_memory2_170 ./work/
+vmap altera_mm_interconnect_170 ./work/
+vmap altera_reset_controller_170 ./work/
+vmap ip_arria10_e1sg_ddr4_4g_1600 ./work/
+vmap altera_emif_arch_nf_170 ./work/
+vmap altera_emif_170 ./work/
+vmap altera_avalon_mm_bridge_170 ./work/
+vmap altera_merlin_slave_translator_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_top.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti_io_aux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_170_6dhhhti.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
+ vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
+ vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
+ vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170_fpxzpei.v" -work altera_emif_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd" -work ip_arria10_e1sg_ddr4_4g_1600
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 38704a1a7ae68ed96aaadf769d6a154242a3b1e7..6512c11b836040ae5b7432084c357bcaaf624ae4 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e9f5251efd88196b161b6af42038a2da80b81b02
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -0,0 +1,95 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+
+vmap altera_merlin_master_translator_170 ./work/
+vmap altera_emif_cal_slave_nf_170 ./work/
+vmap altera_avalon_onchip_memory2_170 ./work/
+vmap ip_arria10_e1sg_ddr4_4g_2000 ./work/
+vmap altera_mm_interconnect_170 ./work/
+vmap altera_reset_controller_170 ./work/
+vmap altera_emif_arch_nf_170 ./work/
+vmap altera_emif_170 ./work/
+vmap altera_avalon_mm_bridge_170 ./work/
+vmap altera_merlin_slave_translator_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_top.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq_io_aux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_170_ctgfmtq.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
+ vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
+ vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
+ vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170_e7aaa3y.v" -work altera_emif_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd" -work ip_arria10_e1sg_ddr4_4g_2000
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index 629af067fcb0844b9a3dd1d7849ffd8a0f46f2a7..b1385a4af07184b21b346f4af23228abd4782eab 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..02d52fa5625bca1174fb4cc3c224bd6e7316f17d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -0,0 +1,125 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+
+vmap ip_arria10_e1sg_ddr4_8g_1600 ./work/
+vmap altera_reset_controller_170 ./work/
+vmap altera_avalon_sc_fifo_170 ./work/
+vmap altera_avalon_st_packets_to_bytes_170 ./work/
+vmap altera_emif_cal_slave_nf_170 ./work/
+vmap altera_merlin_slave_translator_170 ./work/
+vmap altera_emif_170 ./work/
+vmap altera_ip_col_if_170 ./work/
+vmap altera_avalon_onchip_memory2_170 ./work/
+vmap altera_jtag_dc_streaming_170 ./work/
+vmap altera_merlin_master_translator_170 ./work/
+vmap altera_avalon_mm_bridge_170 ./work/
+vmap alt_mem_if_jtag_master_170 ./work/
+vmap altera_emif_arch_nf_170 ./work/
+vmap altera_avalon_st_bytes_to_packets_170 ./work/
+vmap altera_mm_interconnect_170 ./work/
+vmap altera_avalon_packets_to_master_170 ./work/
+vmap channel_adapter_170 ./work/
+vmap timing_adapter_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_top.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei_io_aux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_170_eg5lvei.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_dc_streaming.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_sld_node.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_jtag_streaming.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_clock_crosser.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_std_synchronizer_nocut.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_base.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_remover.v" -work altera_jtag_dc_streaming_170
+ vlog "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_idle_inserter.v" -work altera_jtag_dc_streaming_170
+ vlog -sv "$IP_DIR/../altera_jtag_dc_streaming_170/sim/altera_avalon_st_pipeline_stage.sv" -work altera_jtag_dc_streaming_170
+ vlog -sv "$IP_DIR/../timing_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_170_osazali.sv" -work timing_adapter_170
+ vlog "$IP_DIR/../altera_avalon_sc_fifo_170/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_170
+ vlog "$IP_DIR/../altera_avalon_st_bytes_to_packets_170/sim/altera_avalon_st_bytes_to_packets.v" -work altera_avalon_st_bytes_to_packets_170
+ vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_170/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_170
+ vlog "$IP_DIR/../altera_avalon_packets_to_master_170/sim/altera_avalon_packets_to_master.v" -work altera_avalon_packets_to_master_170
+ vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_bsi6toa.sv" -work channel_adapter_170
+ vlog -sv "$IP_DIR/../channel_adapter_170/sim/ip_arria10_e1sg_ddr4_8g_1600_channel_adapter_170_xbvi4ny.sv" -work channel_adapter_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vcom "$IP_DIR/../alt_mem_if_jtag_master_170/sim/ip_arria10_e1sg_ddr4_8g_1600_alt_mem_if_jtag_master_170_biwt3uq.vhd" -work alt_mem_if_jtag_master_170
+ vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
+ vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_3gbam2q.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_ip_col_if_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_170_bnb3mmy.v" -work altera_ip_col_if_170
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_170_lcqbbfq.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170_zmrgaza.v" -work altera_emif_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd" -work ip_arria10_e1sg_ddr4_8g_1600
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index 5944db188699984646b4f5615d7d5f79e684d46f..21f7c94f81c1858311b0926156c82574e00a294a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..127effe651fffc24467249522d78168aaa37550a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -0,0 +1,95 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+
+vmap altera_merlin_master_translator_170 ./work/
+vmap altera_emif_cal_slave_nf_170 ./work/
+vmap altera_avalon_onchip_memory2_170 ./work/
+vmap ip_arria10_e1sg_ddr4_8g_2400 ./work/
+vmap altera_mm_interconnect_170 ./work/
+vmap altera_reset_controller_170 ./work/
+vmap altera_emif_arch_nf_170 ./work/
+vmap altera_emif_170 ./work/
+vmap altera_avalon_mm_bridge_170 ./work/
+vmap altera_merlin_slave_translator_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_top.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i_io_aux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_170_as3yf3i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_bufs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_se_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_df_o.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_udir_cp_i.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_df.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_bdir_se.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_buf_unused.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_cal_counter.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_fast_sim.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_pll_extra_clks.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_core_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hps_clks_rsts.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_wrap.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_io_tiles_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_abphy_mux.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_avl_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_sideband_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_mmr_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_amm_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_hmc_ast_data_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_afi_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_seq_if.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_emif_arch_nf_regs.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_oct_um_fsm.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_emif_arch_nf_170/sim/altera_std_synchronizer_nocut.v" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/mem_array_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/twentynm_io_12_lane_nf5es_encrypted_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane_bcm__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_170/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_170
+ vlog "$IP_DIR/../altera_avalon_mm_bridge_170/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_170
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd" -work altera_avalon_onchip_memory2_170
+ vlog -sv "$IP_DIR/../altera_merlin_master_translator_170/sim/altera_merlin_master_translator.sv" -work altera_merlin_master_translator_170
+ vlog -sv "$IP_DIR/../altera_merlin_slave_translator_170/sim/mentor/altera_merlin_slave_translator.sv" -work altera_merlin_slave_translator_170
+ vcom "$IP_DIR/../altera_mm_interconnect_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_170_o2ys4ki.vhd" -work altera_mm_interconnect_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_emif_cal_slave_nf_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_170_6qfmevy.v" -work altera_emif_cal_slave_nf_170
+ vlog "$IP_DIR/../altera_emif_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170_xxodvzi.v" -work altera_emif_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd" -work ip_arria10_e1sg_ddr4_8g_2400
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index 1a90c209c7dc0a0838c1c16aedc0c02079bb734f..6bc273c15f80f4c027527f47eea22c8c3553f6d6 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_2400
-hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fifo/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7c8e45e1a1cacbfbd76d13d7c58a0bfbea04b67c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fifo/generated/sim"
+
+vmap ip_arria10_e1sg_fifo_dc_mixed_widths ./work/
+vmap fifo_170 ./work/
+
+
+ vcom "$IP_DIR/../fifo_170/sim/ip_arria10_e1sg_fifo_dc_mixed_widths_fifo_170_kpo7qdy.vhd" -work fifo_170
+ vcom "$IP_DIR/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd" -work ip_arria10_e1sg_fifo_dc_mixed_widths
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index b045f247c54a99e9e74fdab64f4547aa90c3b357..43dbec7e74f945d8c46964bbc2b19b352239f43e 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
-# Copyright (C) 2014
+# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -26,9 +26,14 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+#vlib ./work/ ;# Assume library work already exist
+
+
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
-vmap ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151 ./work/
+vmap altera_asmi_parallel_170 ./work/
+vmap ip_arria10_e1sg_asmi_parallel ./work/
+
-vlog "$IP_DIR/../altera_asmi_parallel_151/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151_27ndfba.v" -work ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
-vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
+ vcom "$IP_DIR/../altera_asmi_parallel_170/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170_eou4tfa.vhd" -work altera_asmi_parallel_170
+ vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd" -work ip_arria10_e1sg_asmi_parallel
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index aeecf8db0a13a74623288cc21ba4ce84c668a432..5a2f5060efb08b6419df7edce487d9514419ffa8 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_asmi_parallel
-hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
+hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 4632c795d4221b696d6a6b907ccfa4d6bc432dfe..0527726f0c2a1312b1914e848367d056fff8c1ce 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
-# Copyright (C) 2014
+# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -26,11 +26,16 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+#vlib ./work/ ;# Assume library work already exist
+
+
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
-vmap ip_arria10_e1sg_remote_update_altera_remote_update_core_151 ./work/
-vmap ip_arria10_e1sg_remote_update_altera_remote_update_151 ./work/
+vmap ip_arria10_e1sg_remote_update ./work/
+vmap altera_remote_update_170 ./work/
+vmap altera_remote_update_core_170 ./work/
+
-vlog "$IP_DIR/../altera_remote_update_core_151/sim/altera_remote_update_core.sv" -work ip_arria10_e1sg_remote_update_altera_remote_update_core_151
-vlog "$IP_DIR/../altera_remote_update_151/sim/ip_arria10_e1sg_remote_update_altera_remote_update_151_fdzfjma.v" -work ip_arria10_e1sg_remote_update_altera_remote_update_151
-vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
+ vlog -sv "$IP_DIR/../altera_remote_update_core_170/sim/mentor/altera_remote_update_core.sv" -work altera_remote_update_core_170
+ vcom "$IP_DIR/../altera_remote_update_170/sim/ip_arria10_e1sg_remote_update_altera_remote_update_170_hsvaqga.vhd" -work altera_remote_update_170
+ vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd" -work ip_arria10_e1sg_remote_update
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 2e9b68cce56238309c5e475b04e8aab3cf8109a2..dbc17122de9c1fd5ce349c500a8730f5d940b81c 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_remote_update
-hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_151
+hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c265887b9b1a33c3a5d82db7274592c956fea16c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generated/sim"
+
+vmap altera_xcvr_fpll_a10_170 ./work/
+vmap ip_arria10_e1sg_fractional_pll_clk125 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd" -work ip_arria10_e1sg_fractional_pll_clk125
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 56be7f5e004a5a69ad2e83203e65d186b85396ea..fabb5c422da8ca1c2799d80e9865e28a00cc0733 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..10c5173cec11c3a2b968e13e8f8e5fd496202722
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generated/sim"
+
+vmap altera_xcvr_fpll_a10_170 ./work/
+vmap ip_arria10_e1sg_fractional_pll_clk200 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd" -work ip_arria10_e1sg_fractional_pll_clk200
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 752ee0e48f66aae3590e43a7e082f0ed7a72b809..6234bd61e1564fbf8fb5efc4a4710c1cc46892cd 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ab612090e521edc5aafaa9e838ebbc7555abe1b8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -0,0 +1,152 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mac_10g/generated/sim"
+
+vmap ip_arria10_e1sg_mac_10g ./work/
+vmap alt_em10g32_170 ./work/
+
+
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/alt_em10g32unit.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_map.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_creg_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii16b_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rr_buffer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_gmii16b_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii_ultra.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_tsu.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_processor.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc_inserter.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/mentor/rtl/alt_em10g32_gmii16b_crc32.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_avalon_dc_fifo.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_dcfifo_synchronizer_bundle.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/alt_em10g32_std_synchronizer.v" -work alt_em10g32_170
+ vlog "$IP_DIR/../alt_em10g32_170/sim/altera_std_synchronizer_nocut.v" -work alt_em10g32_170
+ vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd" -work ip_arria10_e1sg_mac_10g
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index e03e0207f1a7ff892486b764eef1530f476a8982..1d8158eace7f4d417e59f36474491c673f32a824 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_mac_10g
-hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_151
+hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b1f2e646f445271713fc9601d3741904a09bda58
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/mult_add4/generated/sim"
+
+vmap ip_arria10_e1sg_mult_add4 ./work/
+vmap altera_mult_add_170 ./work/
+
+
+ vcom "$IP_DIR/../altera_mult_add_170/sim/ip_arria10_e1sg_mult_add4_altera_mult_add_170_dl6xbqi.vhd" -work altera_mult_add_170
+ vcom "$IP_DIR/ip_arria10_e1sg_mult_add4.vhd" -work ip_arria10_e1sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d8f26c94c00fd311e50c805bdfca71b106003f33
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -0,0 +1,67 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
+
+vmap ip_arria10_e1sg_phy_10gbase_r ./work/
+vmap altera_common_sv_packages ./work/
+vmap altera_xcvr_native_a10_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd" -work ip_arria10_e1sg_phy_10gbase_r
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 74e41675d4ea37c25fcce89ba646f468f7e00c3d..6c840f13a8e5613d968267507c34f016e7d2e452 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..31a4b8ecdf1f4818d5b6eea0bc80b56efea9d2be
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
+
+vmap altera_xcvr_native_a10_170 ./work/
+vmap altera_common_sv_packages ./work/
+vmap ip_arria10_e1sg_phy_10gbase_r_12 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd" -work ip_arria10_e1sg_phy_10gbase_r_12
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index e234ccbd1ea222d958b044f1dbb27446f3bd4939..fe4ed974a93f608227dcc6599f51530074f531c0 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_12
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e9fcebe189677a6c19f60f51e1b9fbeb82c698fd
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
+
+vmap altera_xcvr_native_a10_170 ./work/
+vmap ip_arria10_e1sg_phy_10gbase_r_24 ./work/
+vmap altera_common_sv_packages ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd" -work ip_arria10_e1sg_phy_10gbase_r_24
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 36af90e16d4089860a8581ffb390ec1f2e265bff..b98242ff86d1d05f38e9cc7da41bafc2e8c38f87 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4fe8425929233b7c0cfc449bca9eede1a350f4b4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
+
+vmap altera_xcvr_native_a10_170 ./work/
+vmap ip_arria10_e1sg_phy_10gbase_r_4 ./work/
+vmap altera_common_sv_packages ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd" -work ip_arria10_e1sg_phy_10gbase_r_4
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 680f6a38677c847b79186ea491ca3e52dae2df2b..5bd9766c675c13505c303f558647a186d9ce8cb7 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_4
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..62ebc5f3090792f7e6b8c51dd875a7369f4dccf4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -0,0 +1,68 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generated/sim"
+
+vmap ip_arria10_e1sg_phy_10gbase_r_48 ./work/
+vmap altera_xcvr_native_a10_170 ./work/
+vmap altera_common_sv_packages ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd" -work ip_arria10_e1sg_phy_10gbase_r_48
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 977dbcf2d24e4b9ed0a38b3de63db4e4b5dad870..885cf69d658ddc0f5a2a15a240f16be5a2d0652d 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_48
-hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f1e8cc9651cc4245b43db7c6574d38f093b1b6ff
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk125/generated/sim"
+
+vmap altera_iopll_170 ./work/
+vmap ip_arria10_e1sg_pll_clk125 ./work/
+
+
+ vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_170_3a4ewza.vo" -work altera_iopll_170
+ vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd" -work ip_arria10_e1sg_pll_clk125
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 3b93d5e09ca59cc7b52c90ef4fb54899f1ebfdaf..27d139d060e66265fb7327cd9187bd31b4b6ac4a 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk125
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_151
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..46d78c00ae79b5ce98ad1156860329f8bc8e687c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk200/generated/sim"
+
+vmap altera_iopll_170 ./work/
+vmap ip_arria10_e1sg_pll_clk200 ./work/
+
+
+ vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_170_bqwoevq.vo" -work altera_iopll_170
+ vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd" -work ip_arria10_e1sg_pll_clk200
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 99e5895aceb644a201a288db39ab44216460dab7..8354a6cd568011264233de7f791cb78b4767698b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk200
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_151
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f07d13f9a8767e3a9f2788c25220c790ba939a98
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_clk25/generated/sim"
+
+vmap altera_iopll_170 ./work/
+vmap ip_arria10_e1sg_pll_clk25 ./work/
+
+
+ vlog "$IP_DIR/../altera_iopll_170/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_170_7lq52ua.vo" -work altera_iopll_170
+ vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd" -work ip_arria10_e1sg_pll_clk25
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index 63bd14dfd32eb1abe8838e751bcdc92eedf0a862..36c560f4815a5cdaf4e7135accc1364f0e7d86d4 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_pll_clk25
-hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_151
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5f9efe2553284d70d26bc61ba5ec957caa9e2f82
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -0,0 +1,50 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generated/sim"
+
+vmap ip_arria10_e1sg_pll_xgmii_mac_clocks ./work/
+vmap altera_xcvr_fpll_a10_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/altera_xcvr_fpll_a10.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/a10_avmm_h.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_native_avmm_nf.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work altera_xcvr_fpll_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_fpll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work altera_xcvr_fpll_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd" -work ip_arria10_e1sg_pll_xgmii_mac_clocks
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index 3e585d95929ab27cb38a4413369274ceab9a16fe..5ffbb7605059429241e2a9c626efc8880d4f30cf 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_pll_xgmii_mac_clocks
-hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/ram/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ram/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6343eb8921630585c4aa39789de15bde76818f86
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ram/generated/sim"
+
+vmap ip_arria10_e1sg_ram_r_w ./work/
+vmap ram_2port_170 ./work/
+
+
+ vcom "$IP_DIR/../ram_2port_170/sim/ip_arria10_e1sg_ram_r_w_ram_2port_170_dddfrrq.vhd" -work ram_2port_170
+ vcom "$IP_DIR/ip_arria10_e1sg_ram_r_w.vhd" -work ip_arria10_e1sg_ram_r_w
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d1a9ff5c98815abe015ce01d708e608a62705bf1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/temp_sense/generated/sim"
+
+vmap altera_temp_sense_170 ./work/
+vmap ip_arria10_e1sg_temp_sense ./work/
+
+
+ vlog "$IP_DIR/../altera_temp_sense_170/sim/altera_temp_sense.v" -work altera_temp_sense_170
+ vcom "$IP_DIR/ip_arria10_e1sg_temp_sense.vhd" -work ip_arria10_e1sg_temp_sense
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 26d451acdfc1cc2b4ef2c68165db2f5c6b6457d3..7b8c823272ab874c573033a7dcd8b52c4c9efcc6 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_temp_sense
-hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_151
+hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b50bf327171a641d6d3051822ceaa49e34ab431e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -0,0 +1,57 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generated/sim"
+
+vmap ip_arria10_e1sg_transceiver_pll_10g ./work/
+vmap altera_common_sv_packages ./work/
+vmap altera_xcvr_atx_pll_a10_170 ./work/
+
+
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_atx_pll_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vlog -sv {"+incdir+$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/reconfig/"} "$IP_DIR/../altera_xcvr_atx_pll_a10_170/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd" -work ip_arria10_e1sg_transceiver_pll_10g
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index f89384011679be01f6822d6fc3e350023dfe6c81..4fc3cf835ebb30b74957209f24e20de2d462ab75 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4a5da10cc8b4db878d4bdacb6c53f8765bca2240
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generated/sim"
+
+vmap ip_arria10_e1sg_transceiver_reset_controller_1 ./work/
+vmap altera_xcvr_reset_control_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd" -work ip_arria10_e1sg_transceiver_reset_controller_1
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 130feaaeb93c92d94b9c808796d2f5eaa81fb19a..b4ed24e8fbb496bd54208a31a470b07b8fbfb424 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5cb1f82a1d365c5f5f6dee9a677759ee7f6d0329
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generated/sim"
+
+vmap altera_xcvr_reset_control_170 ./work/
+vmap ip_arria10_e1sg_transceiver_reset_controller_12 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd" -work ip_arria10_e1sg_transceiver_reset_controller_12
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index fa572fc2d5df2f8bcf9b50f552206f617a899343..95fa7b95d30bb0372aaf91d05a70a0fed649f17a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_12
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..02ab0f4ebffa9b39126d84b0ed2b7301933bb0d1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generated/sim"
+
+vmap altera_xcvr_reset_control_170 ./work/
+vmap ip_arria10_e1sg_transceiver_reset_controller_24 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd" -work ip_arria10_e1sg_transceiver_reset_controller_24
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 47c738e840d9f34735654480297ad0f19cdb0f2c..edcc1db84e4c3f7e87a21e5fe8db33b56fce17b6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fc9acd4d40ce20dbe700c6e9e7eac9bb4b302f97
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generated/sim"
+
+vmap ip_arria10_e1sg_transceiver_reset_controller_4 ./work/
+vmap altera_xcvr_reset_control_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd" -work ip_arria10_e1sg_transceiver_reset_controller_4
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index e1a30e6660020843261a2525ab540cd34a6060f0..8e5a0b5fe364456e1b93e592ee6301977b6206ab 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_4
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..15697051bbbdb7252d49c785ad65768fc7749607
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generated/sim"
+
+vmap altera_xcvr_reset_control_170 ./work/
+vmap ip_arria10_e1sg_transceiver_reset_controller_48 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_functions.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_resync.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/altera_xcvr_reset_control.sv" -work altera_xcvr_reset_control_170
+ vlog -sv "$IP_DIR/../altera_xcvr_reset_control_170/sim/mentor/alt_xcvr_reset_counter.sv" -work altera_xcvr_reset_control_170
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd" -work ip_arria10_e1sg_transceiver_reset_controller_48
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index ded13eeaff2b64887a39364b97e3c113c8736360..70912eb470eab7a79c6ff15282cab08fdcd00579 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_48
-hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6a99c5951cf24329f749bcab310acc551b518342
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -0,0 +1,270 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
+
+vmap altera_xcvr_native_a10_170 ./work/
+vmap altera_eth_tse_170 ./work/
+vmap altera_eth_tse_mac_170 ./work/
+vmap altera_reset_controller_170 ./work/
+vmap altera_eth_tse_nf_phyip_terminator_170 ./work/
+vmap altera_eth_tse_avalon_arbiter_170 ./work/
+vmap altera_common_sv_packages ./work/
+vmap altera_eth_tse_pcs_pma_nf_phyip_170 ./work/
+vmap ip_arria10_e1sg_tse_sgmii_gx ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_stage.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_pcs_pma_nf_phyip.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_sequencer.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_ctrl_lego.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_xcvr_resync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gxb_aligned_rxsync.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ph_calculator.sv" -L altera_common_sv_packages -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_phyip_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_170_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_170/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_phyip_terminator_170/sim/mentor/altera_eth_tse_nf_phyip_terminator.v" -work altera_eth_tse_nf_phyip_terminator_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170_bs6nd6i.vhd" -work altera_eth_tse_170
+ vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd" -work ip_arria10_e1sg_tse_sgmii_gx
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index b1b572504b80e2690b82c6c3ce4534c00ed15faf..97f2f186472d0c7f835228825052de6eaca1b33a 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..60279e5ca1275a46e4e557d88e7ab3b62ed016e9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -0,0 +1,256 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generated/sim"
+
+vmap altera_reset_controller_170 ./work/
+vmap altera_eth_tse_pcs_pma_nf_lvds_170 ./work/
+vmap altera_eth_tse_mac_170 ./work/
+vmap altera_eth_tse_nf_lvds_terminator_170 ./work/
+vmap altera_eth_tse_170 ./work/
+vmap ip_arria10_e1sg_tse_sgmii_lvds ./work/
+vmap altera_lvds_core20_170 ./work/
+vmap altera_eth_tse_avalon_arbiter_170 ./work/
+vmap altera_lvds_170 ./work/
+
+
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_mac.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clk_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328checker.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc328generator.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32ctl8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_crc32galois8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gmii_io.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_read_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lb_wrt_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_hashing.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_host_control_small.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_register_map_small.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_counter_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_mac_control.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_shared_register_map.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_counter_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_lfsr_10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_loopback_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altshifttaps.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_rx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_rx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_mac_tx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mac_tx.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_magic_detection.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_clk_gen.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mdio_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_mdio.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_rx_if.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_mii_tx_if.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_base.v" -work altera_eth_tse_mac_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_pipeline_stage.sv" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_16x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_8x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_dpram_ecc_16x32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_fifoless_retransmit_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_retransmit_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in1.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_in4.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_nf_rgmii_module.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_module.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out1.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rgmii_out4.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_min_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_ff_length.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_rx_stat_extract.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_timing_adapter_fifo8.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_1geth.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_fifoless_1geth.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_w_fifo_10_100_1000.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_wo_fifo_10_100_1000.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_top_gen_host.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_min_ff.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_cntrl_32_shift16.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_length.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_ff_read_cntl.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_tx_stat_extract.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_mac_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_mac_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_mac_170
+ vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_170/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_pcs_pma_nf_lvds.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_align_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec10b8b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_dec_func.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_encapsulation_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pcs_host_control.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mdio_reg.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_rx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_mii_tx_if_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_sync.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sgmii_clk_cntl.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_colision_detect.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_rx_fifo_rd.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_sgmii_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_tx_converter.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_1000_base_x_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_pcs_strx_gx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_top_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reset_sequencer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_lvds_reverse_loopback.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx_av.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_rx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_pma_lvds_tx.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_std_synchronizer_bundle.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_eth_tse_ptp_std_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_false_path_marker.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_clock_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_13.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_24.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_34.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_1246.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_14_44.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_a_fifo_opt_36_10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_gray_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_altsyncram.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_altsyncram_dpm_fifo.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_bin_cnt.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog -sv "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ph_calculator.sv" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_sdpm_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x10_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x14_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x2_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x23_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x36_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x40_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_dec_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_enc_x30_wrapper.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/mentor/altera_tse_ecc_status_crosser.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_pcs_pma_nf_lvds_170
+ vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170
+ vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170
+ vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_qagiwoa.vhd" -work altera_lvds_core20_170
+ vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_m5pqrlq.vhd" -work altera_lvds_170
+ vlog -sv "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_170
+ vlog "$IP_DIR/../altera_lvds_core20_170/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_170
+ vcom "$IP_DIR/../altera_lvds_core20_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_170_o4ldvbi.vhd" -work altera_lvds_core20_170
+ vcom "$IP_DIR/../altera_lvds_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_170_o42lhkq.vhd" -work altera_lvds_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_std_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_eth_tse_nf_lvds_terminator.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_reset_synchronizer.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_channel_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/mentor/altera_tse_nf_lvds_common_reset_sequencer.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_eth_tse_nf_lvds_terminator_170/sim/altera_std_synchronizer_nocut.v" -work altera_eth_tse_nf_lvds_terminator_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_170
+ vlog "$IP_DIR/../altera_reset_controller_170/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_170
+ vcom "$IP_DIR/../altera_eth_tse_170/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170_kv2t7sq.vhd" -work altera_eth_tse_170
+ vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd" -work ip_arria10_e1sg_tse_sgmii_lvds
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 8b7150fdc0e6f33da1141ca02576e8a130a41bac..044645662000ff6087e2c8507e3a0ab8ddb96426 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..74b7f80f1796e9331ced14130c8021a972ef279e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -0,0 +1,47 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/voltage_sense/generated/sim"
+
+vmap ip_arria10_e1sg_voltage_sense ./work/
+vmap altera_voltage_sensor_170 ./work/
+vmap altera_voltage_sensor_control_170 ./work/
+vmap altera_voltage_sensor_sample_store_170 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_170/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_170
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_170/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_170
+ vcom "$IP_DIR/../altera_voltage_sensor_170/sim/ip_arria10_e1sg_voltage_sense_altera_voltage_sensor_170_hjr63vq.vhd" -work altera_voltage_sensor_170
+ vcom "$IP_DIR/ip_arria10_e1sg_voltage_sense.vhd" -work ip_arria10_e1sg_voltage_sense
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 4cd22866aae4fe8db79559111d5f0bdd2728a66d..fb423817ca925ad3cbdd8a877212a81e77ac44ae 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_e1sg_voltage_sense
-hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
+hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg