instantiated bsn_source_v2

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -40,7 +40,7 @@ ENTITY node_sdp_adc_input_and_timing IS
   GENERIC (
     g_technology              : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data            : NATURAL := c_sdp_V_si_db;
-    g_bsn_sync_timeout        : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
+    g_bsn_nof_clk_per_sync    : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
     g_sim                     : BOOLEAN := FALSE  
   );
   PORT (
@@ -237,11 +237,11 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Timestamp
   -----------------------------------------------------------------------------  
-  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
+  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source_v2
   GENERIC MAP (
     g_cross_clock_domain     => TRUE,
     g_block_size             => c_bs_block_size,
-    g_nof_block_per_sync     => c_bs_nof_block_per_sync,
+    g_nof_clk_per_sync       => g_bsn_nof_clk_per_sync,
     g_bsn_w                  => c_bs_bsn_w
   )
   PORT MAP (
@@ -367,7 +367,7 @@ BEGIN
   u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
   GENERIC MAP (
     g_nof_streams        => 1,  -- They're all the same
-    g_sync_timeout       => g_bsn_sync_timeout,
+    g_sync_timeout       => g_bsn_nof_clk_per_sync,
     g_bsn_w              => c_bs_bsn_w,
     g_log_first_bsn      => FALSE
   )

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -150,7 +150,7 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_reg_wg_addr_w                 : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
   CONSTANT c_sdp_ram_wg_addr_w                 : NATURAL := 10 + ceil_log2(c_sdp_S_pn); 
   CONSTANT c_sdp_reg_dp_shiftram_addr_w        : NATURAL := 1 + ceil_log2(c_sdp_S_pn); 
-  CONSTANT c_sdp_reg_bsn_source_addr_w         : NATURAL := 2;
+  CONSTANT c_sdp_reg_bsn_source_addr_w         : NATURAL := 2; -- TODO +1 due to bsn_source_v2
   CONSTANT c_sdp_reg_bsn_scheduler_addr_w      : NATURAL := 1;
   CONSTANT c_sdp_ram_diag_data_buf_jesd_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db);
   CONSTANT c_sdp_reg_diag_data_buf_jesd_addr_w : NATURAL := 1 + ceil_log2(2);