diff --git a/tools/quartus/run_altera_simlib_comp b/tools/quartus/run_altera_simlib_comp index 1f165c48acde51590c90f741922c4d7a940aac40..1f7dde5d2b96d0182d5c9a962751295170f0e665 100755 --- a/tools/quartus/run_altera_simlib_comp +++ b/tools/quartus/run_altera_simlib_comp @@ -123,8 +123,10 @@ mv ../${FAMILY}_vhdl.log . # # file.txt = the file name -sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do -sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do +if [ "${TARGET}" = "unb2" ]; then + sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do + sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do +fi # 4) Compile the Altera libraries with Modelsim $VSIM_DIR/vsim -c -do ${FAMILY}_verilog.do