diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index f0cb496d1fe23a6c5fb84c87b9706ee7340c5023..bbee8220686a43f21b82e8164bcd99f36d0020b1 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_dc IS
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index a5f0be0f914515421e7857451f3bb3da31ede156..9912a6a20afd9c674b495f7671bbf4f3b1a49cb5 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_dc_mixed_widths IS
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 726e959439713fc5209cc9cecee1b6bf6274b690..7481ddeed25fdb4170287f946acf66ef1d10c6ce 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_sc IS
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index e33f8724245782d2535bfd3dac4c9cfe3eacfe95..2ad7f8121b8ce1cfd683fb5eaef0f315849d9455 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_flash_lib;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index d05e8a0b5039c868edc7e218640fb5220d007748..52b2701ce8b163e8cd1aa29a52e130ced5968e29 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_flash_lib;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 114cb7f59706c2d84bb8ddd7b9d28de89b9eeb57..252f592c2e1ddd8161489bc68eafd4f248dea1db 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
 
 ENTITY tech_iobuf_ddio_in IS
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 36a747ba586117d0d31228c04131c34b19c84b86..efbf517b736b9577b4766a7cb73cc8f598e44f8c 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
 
 ENTITY tech_iobuf_ddio_out IS
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 840b84c331f1c4073a8745b765337ab488c1a585..a827d21b3547a08110a00174a61a2f6fb6df016a 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 146109bf51edf0391078655373bf49b567320fa5..713ec891a298b933c8b257ad31b55301e7091497 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index f109e871eb4c8b40ff6afa22001896b5c5d8f2c0..90d31e97149da78d89606fa4fab017224e9f312f 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 3505b8f7fff716376f45de9ba490ba503cd6f686..babfc362fce72ecb91edf62c1deb415d90e5de7c 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_r_w IS
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 69aa54a2cd818a816059a6ea648a221360055532..d959b639169da22766b773a72f1b465542214b44 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_rom_r IS
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index 5e4c146c2a80035faadfb7a130de3adbd878977f..e6425c1414b042af494791423229bfa396b8d3e7 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_transceiver_lib;
 
 LIBRARY IEEE, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;