Skip to content
Snippets Groups Projects
Commit cce30a20 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Only support RTL archictecture. No need to port Megawizard arch...

Only support RTL archictecture. No need to port Megawizard arch dsp_mult_add2,4.vhd from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk.
parent 42bdc3c3
No related branches found
No related tags found
No related merge requests found
...@@ -37,9 +37,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -37,9 +37,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- --
-- Architectures: -- Architectures:
-- . rtl : uses RTL to have all registers in one clocked process -- . rtl : uses RTL to have all registers in one clocked process
-- . stratix4 : uses MegaWizard component dsp_mult_add2.vhd
-- --
-- Preferred architecture: 'stratix4', see synth\quartus\common_top.vhd
ENTITY common_mult_add2 IS ENTITY common_mult_add2 IS
GENERIC ( GENERIC (
......
...@@ -40,9 +40,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -40,9 +40,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- --
-- Architectures: -- Architectures:
-- . rtl : uses RTL to have all registers in one clocked process -- . rtl : uses RTL to have all registers in one clocked process
-- . stratix4 : uses MegaWizard component dsp_mult_add4.vhd
-- --
-- Preferred architecture: 'rtl', see synth\quartus\common_top.vhd
ENTITY common_mult_add4 IS ENTITY common_mult_add4 IS
GENERIC ( GENERIC (
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment