diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 7169df71b37949241bca0264e769bbec9de38015..9a32e5b6c5e487c83a96b0c31d8a5e98b94e76de 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -37,9 +37,7 @@ USE technology_lib.technology_select_pkg.ALL;
 --
 -- Architectures:
 -- . rtl      : uses RTL to have all registers in one clocked process
--- . stratix4 : uses MegaWizard component dsp_mult_add2.vhd
 --
--- Preferred architecture: 'stratix4', see synth\quartus\common_top.vhd
 
 ENTITY common_mult_add2 IS
   GENERIC (
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index aa3a0952e38a60ab83880a2d540a07aba7fb4903..5bb8605056086f3b4c90ff93d109aa3751c9e7ad 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -40,9 +40,7 @@ USE technology_lib.technology_select_pkg.ALL;
 --
 -- Architectures:
 -- . rtl      : uses RTL to have all registers in one clocked process
--- . stratix4 : uses MegaWizard component dsp_mult_add4.vhd
 --
--- Preferred architecture: 'rtl', see synth\quartus\common_top.vhd
 
 ENTITY common_mult_add4 IS
   GENERIC (