10GbE additions for unb2

boards/uniboard2/designs/unb2_test/hdllib.cfg

 hdl_lib_name = unb2_test
 hdl_library_clause_name = unb2_test_lib
-hdl_lib_uses = common mm unb2_board 
+#hdl_lib_uses = common mm unb2_board 
+hdl_lib_uses = common technology mm unb2_board dp eth tech_tse tr_10GbE diagnostics diag
 hdl_lib_technology = ip_arria10
 
+
+
 build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
@@ -18,6 +21,15 @@ synth_top_level_entity =
 
 quartus_copy_files =
     quartus/qsys_unb2_test.qsys .
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex ../..
+    $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex ../..
 
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf

boards/uniboard2/designs/unb2_test/src/hex/default_eth_header.hex

+:0800000000074306C7000022BF
+:0800010086080000080045001C
+:080002002322000040007F11E1
+:08000300BA530A6300010A0A66
+:080004000A0A0FA00FA0230E51
+:080005000000000000000000F3
+:080006000000000000000000F2
+:080007000000000000000000F1
+:00000001FF

boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd

@@ -24,18 +24,30 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL; --?
+USE common_lib.common_field_pkg.ALL; --?
+USE common_lib.common_network_total_header_pkg.ALL; --?
+USE common_lib.common_network_layers_pkg.ALL; --?
 USE unb2_board_lib.unb2_board_pkg.ALL;
 USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
+--USE eth_lib.eth_pkg.ALL; --?
+--USE technology_lib.technology_pkg.ALL; --?
+--USE tech_tse_lib.tech_tse_pkg.ALL; --?
+--USE tech_tse_lib.tb_tech_tse_pkg.ALL; --?
 USE work.qsys_unb2_test_pkg.ALL;
 
 
+
 ENTITY mmm_unb2_test IS
   GENERIC (
     g_sim         : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
     g_sim_unb_nr  : NATURAL := 0;
-    g_sim_node_nr : NATURAL := 0
+    g_sim_node_nr : NATURAL := 0;
+    g_nof_streams   : NATURAL;
+    g_bg_block_size : NATURAL;
+    g_hdr_field_arr : t_common_field_arr
   );
   PORT (
     mm_rst                   : IN  STD_LOGIC;
@@ -69,6 +81,7 @@ ENTITY mmm_unb2_test IS
     eth1g_reg_interrupt      : IN  STD_LOGIC; 
     eth1g_ram_mosi           : OUT t_mem_mosi;  
     eth1g_ram_miso           : IN  t_mem_miso;
+
     -- EPCS read
     reg_dpmm_data_mosi       : OUT t_mem_mosi;
     reg_dpmm_data_miso       : IN  t_mem_miso;
@@ -87,7 +100,40 @@ ENTITY mmm_unb2_test IS
 
     -- Remote Update
     reg_remu_mosi            : OUT t_mem_mosi;
-    reg_remu_miso            : IN  t_mem_miso
+    reg_remu_miso            : IN  t_mem_miso;
+
+    -- bg
+    ram_diag_bg_mosi               : OUT t_mem_mosi;
+    ram_diag_bg_miso               : IN  t_mem_miso;
+    reg_diag_bg_mosi               : OUT t_mem_mosi;
+    reg_diag_bg_miso               : IN  t_mem_miso;
+
+    -- dp offload
+    reg_dp_offload_tx_mosi         : OUT t_mem_mosi;
+    reg_dp_offload_tx_miso         : IN  t_mem_miso;
+
+    reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+    reg_dp_offload_tx_hdr_dat_miso : IN  t_mem_miso;
+
+    reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
+    reg_dp_offload_tx_hdr_ovr_miso : IN  t_mem_miso;
+
+    reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
+    reg_dp_offload_rx_hdr_dat_miso : IN  t_mem_miso;
+
+    -- bsn monitor
+    reg_bsn_monitor_mosi           : OUT t_mem_mosi;
+    reg_bsn_monitor_miso           : IN  t_mem_miso;
+
+    -- db
+    ram_diag_data_buf_mosi         : OUT t_mem_mosi;
+    ram_diag_data_buf_miso         : IN  t_mem_miso;
+    reg_diag_data_buf_mosi         : OUT t_mem_mosi;
+    reg_diag_data_buf_miso         : IN  t_mem_miso;
+
+    -- 10GbE
+    reg_tr_10GbE_mosi              : OUT t_mem_mosi;
+    reg_tr_10GbE_miso              : IN  t_mem_miso
   );
 END mmm_unb2_test;
 
@@ -96,6 +142,46 @@ ARCHITECTURE str OF mmm_unb2_test IS
   CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
   CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
 
+  -- Block generator
+  CONSTANT c_ram_diag_bg_addr_w                    : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
+
+  -- dp_offload
+  CONSTANT c_reg_dp_offload_tx_adr_w               : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+  CONSTANT c_reg_dp_offload_tx_multi_adr_w         : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
+
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words   : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
+
+  CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words   : NATURAL := g_hdr_field_arr'LENGTH;
+  CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
+  CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
+
+  CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words   : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
+  CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w       : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
+  CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
+
+  -- tr_10GbE
+  CONSTANT c_reg_tr_10GbE_adr_w                    : NATURAL := 13;
+  CONSTANT c_reg_tr_10GbE_multi_adr_w              : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_tr_10GbE_adr_w));
+
+  -- BSN monitors
+  CONSTANT c_reg_rsp_bsn_monitor_adr_w             : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+
+  -- Simulation
+  CONSTANT c_mm_clk_period                         : TIME := 8 ns;   -- 125 MHz
+
+  CONSTANT c_sim_eth_src_mac                       : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+  --CONSTANT c_sim_eth_control_rx_en                 : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+  SIGNAL sim_eth_mm_bus_switch                     : STD_LOGIC;
+  SIGNAL sim_eth_psc_access                        : STD_LOGIC;
+
+  SIGNAL i_eth1g_reg_mosi                          : t_mem_mosi;
+  SIGNAL i_eth1g_reg_miso                          : t_mem_miso;
+
+  SIGNAL sim_eth1g_reg_mosi                        : t_mem_mosi;
+
   ----------------------------------------------------------------------------
   -- mm_file component
   ----------------------------------------------------------------------------
@@ -135,10 +221,70 @@ BEGIN
     u_mm_file_reg_ppsh            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
                                                PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
 
+    u_mm_file_reg_diag_bg               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+                                                     PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+    u_mm_file_ram_diag_bg               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+                                                     PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+    u_mm_file_reg_dp_offload_tx         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+
+    u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+
+    u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+
+    u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+                                                     PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+
+    u_mm_file_reg_bsn_monitor           : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+                                                     PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+    u_mm_file_ram_diag_data_buffer      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+                                                     PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+    u_mm_file_reg_diag_data_buffer      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+                                                     PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
     -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
     u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
                                                PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
 
+    --u_mm_file_reg_tr_10GbE        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
+    --                                           PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+
+    ----------------------------------------------------------------------------
+    -- 1GbE setup sequence normally performed by unb_os@NIOS
+    ----------------------------------------------------------------------------
+    p_eth_setup : PROCESS
+    BEGIN
+      sim_eth_mm_bus_switch <= '1';
+
+      eth1g_tse_mosi.wr <= '0';
+      eth1g_tse_mosi.rd <= '0';
+      WAIT FOR 400 ns;
+      WAIT UNTIL rising_edge(mm_clk);
+ --     proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+
+      -- Enable RX
+--      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);  -- control rx en
+      sim_eth_mm_bus_switch <= '0';
+
+      WAIT;
+    END PROCESS;
+
+    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+    BEGIN
+      IF sim_eth_mm_bus_switch = '1' THEN
+          eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+        ELSE
+          eth1g_reg_mosi <= i_eth1g_reg_mosi;
+        END IF;
+    END PROCESS;
+
+
     ----------------------------------------------------------------------------
     -- Procedure that polls a sim control file that can be used to e.g. get
     -- the simulation time in ns
@@ -157,8 +303,6 @@ BEGIN
       clk_clk                                   => mm_clk,
       reset_reset_n                             => mm_rst,
 
-      pio_debug_wave_external_connection_export => OPEN,
-
       -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
       pio_wdi_external_connection_export        => pout_wdi,
 
@@ -268,7 +412,88 @@ BEGIN
       reg_mmdp_ctrl_read_export                 => reg_mmdp_ctrl_mosi.rd,
       reg_mmdp_ctrl_readdata_export             => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
       reg_mmdp_ctrl_write_export                => reg_mmdp_ctrl_mosi.wr,
-      reg_mmdp_ctrl_writedata_export            => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+      reg_mmdp_ctrl_writedata_export            => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_tr_10gbe_reset_export                 => OPEN,
+      reg_tr_10gbe_clk_export                   => OPEN,
+      reg_tr_10gbe_address_export               => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
+      reg_tr_10gbe_write_export                 => reg_tr_10GbE_mosi.wr,
+      reg_tr_10gbe_writedata_export             => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_tr_10gbe_read_export                  => reg_tr_10GbE_mosi.rd,
+      reg_tr_10gbe_readdata_export              => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_tr_10gbe_waitrequest_export           => reg_tr_10GbE_miso.waitrequest,
+
+      reg_bsn_monitor_reset_export              => OPEN,
+      reg_bsn_monitor_clk_export                => OPEN,
+      reg_bsn_monitor_address_export            => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
+      reg_bsn_monitor_write_export              => reg_bsn_monitor_mosi.wr,
+      reg_bsn_monitor_writedata_export          => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_bsn_monitor_read_export               => reg_bsn_monitor_mosi.rd,
+      reg_bsn_monitor_readdata_export           => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_offload_tx_reset_export            => OPEN,
+      reg_dp_offload_tx_clk_export              => OPEN,
+      reg_dp_offload_tx_address_export          => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_write_export            => reg_dp_offload_tx_mosi.wr,
+      reg_dp_offload_tx_writedata_export        => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_read_export             => reg_dp_offload_tx_mosi.rd,
+      reg_dp_offload_tx_readdata_export         => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_offload_tx_hdr_dat_reset_export     => OPEN,
+      reg_dp_offload_tx_hdr_dat_clk_export       => OPEN,
+      reg_dp_offload_tx_hdr_dat_address_export   => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_dat_write_export     => reg_dp_offload_tx_hdr_dat_mosi.wr,
+      reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_dat_read_export      => reg_dp_offload_tx_hdr_dat_mosi.rd,
+      reg_dp_offload_tx_hdr_dat_readdata_export  => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_offload_rx_hdr_dat_reset_export     => OPEN,
+      reg_dp_offload_rx_hdr_dat_clk_export       => OPEN,
+      reg_dp_offload_rx_hdr_dat_address_export   => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_rx_hdr_dat_write_export     => reg_dp_offload_rx_hdr_dat_mosi.wr,
+      reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_rx_hdr_dat_read_export      => reg_dp_offload_rx_hdr_dat_mosi.rd,
+      reg_dp_offload_rx_hdr_dat_readdata_export  => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_offload_tx_hdr_ovr_reset_export     => OPEN,
+      reg_dp_offload_tx_hdr_ovr_clk_export       => OPEN,
+      reg_dp_offload_tx_hdr_ovr_address_export   => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_ovr_write_export     => reg_dp_offload_tx_hdr_ovr_mosi.wr,
+      reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_dp_offload_tx_hdr_ovr_read_export      => reg_dp_offload_tx_hdr_ovr_mosi.rd,
+      reg_dp_offload_tx_hdr_ovr_readdata_export  => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_diag_data_buffer_reset_export          => OPEN,
+      reg_diag_data_buffer_clk_export            => OPEN,
+      reg_diag_data_buffer_address_export        => reg_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+      reg_diag_data_buffer_write_export          => reg_diag_data_buf_mosi.wr,
+      reg_diag_data_buffer_writedata_export      => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_diag_data_buffer_read_export           => reg_diag_data_buf_mosi.rd,
+      reg_diag_data_buffer_readdata_export       => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      ram_diag_data_buffer_clk_export            => OPEN,
+      ram_diag_data_buffer_reset_export          => OPEN,
+      ram_diag_data_buffer_address_export        => ram_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+      ram_diag_data_buffer_write_export          => ram_diag_data_buf_mosi.wr,
+      ram_diag_data_buffer_writedata_export      => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_diag_data_buffer_read_export           => ram_diag_data_buf_mosi.rd,
+      ram_diag_data_buffer_readdata_export       => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_diag_bg_reset_export                   => OPEN,
+      reg_diag_bg_clk_export                     => OPEN,
+      reg_diag_bg_address_export                 => reg_diag_bg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+      reg_diag_bg_write_export                   => reg_diag_bg_mosi.wr,
+      reg_diag_bg_writedata_export               => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_diag_bg_read_export                    => reg_diag_bg_mosi.rd,
+      reg_diag_bg_readdata_export                => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      ram_diag_bg_reset_export                   => OPEN,
+      ram_diag_bg_clk_export                     => OPEN,
+      ram_diag_bg_address_export                 => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
+      ram_diag_bg_write_export                   => ram_diag_bg_mosi.wr,
+      ram_diag_bg_writedata_export               => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_diag_bg_read_export                    => ram_diag_bg_mosi.rd,
+      ram_diag_bg_readdata_export                => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0)
       );
   END GENERATE;
 

boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd

@@ -32,7 +32,6 @@ PACKAGE qsys_unb2_test_pkg IS
         port (
             clk_clk                                   : in  std_logic                     := 'X';             -- clk
             reset_reset_n                             : in  std_logic                     := 'X';             -- reset_n
-            pio_debug_wave_external_connection_export : out std_logic_vector(31 downto 0);                    -- export
             pio_wdi_external_connection_export        : out std_logic;                                        -- export
             avs_eth_0_reset_export                    : out std_logic;                                        -- export
             avs_eth_0_clk_export                      : out std_logic;                                        -- export
@@ -129,7 +128,78 @@ PACKAGE qsys_unb2_test_pkg IS
             reg_dpmm_data_write_export                : out std_logic;                                        -- export
             reg_dpmm_data_address_export              : out std_logic;--_vector(0 downto 0);                     -- export
             reg_dpmm_data_clk_export                  : out std_logic;                                        -- export
-            reg_dpmm_data_reset_export                : out std_logic                                         -- export
+            reg_dpmm_data_reset_export                : out std_logic;                                        -- export
+            reg_tr_10gbe_reset_export                 : out std_logic;                                        -- export
+            reg_tr_10gbe_clk_export                   : out std_logic;                                        -- export
+            reg_tr_10gbe_address_export               : out std_logic_vector(14 downto 0);                    -- export
+            reg_tr_10gbe_write_export                 : out std_logic;                                        -- export
+            reg_tr_10gbe_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
+            reg_tr_10gbe_read_export                  : out std_logic;                                        -- export
+            reg_tr_10gbe_readdata_export              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_tr_10gbe_waitrequest_export           : in  std_logic                     := 'X';             -- export
+            reg_bsn_monitor_reset_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_clk_export                : out std_logic;                                        -- export
+            reg_bsn_monitor_address_export            : out std_logic_vector(5 downto 0);                     -- export
+            reg_bsn_monitor_write_export              : out std_logic;                                        -- export
+            reg_bsn_monitor_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            reg_bsn_monitor_read_export               : out std_logic;                                        -- export
+            reg_bsn_monitor_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_tx_reset_export            : out std_logic;                                        -- export
+            reg_dp_offload_tx_clk_export              : out std_logic;                                        -- export
+            reg_dp_offload_tx_address_export          : out std_logic_vector(2 downto 0);                     -- export
+            reg_dp_offload_tx_write_export            : out std_logic;                                        -- export
+            reg_dp_offload_tx_writedata_export        : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_tx_read_export             : out std_logic;                                        -- export
+            reg_dp_offload_tx_readdata_export         : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_tx_hdr_dat_reset_export    : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_dat_clk_export      : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_dat_address_export  : out std_logic_vector(7 downto 0);                     -- export
+            reg_dp_offload_tx_hdr_dat_write_export    : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_tx_hdr_dat_read_export      : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_dat_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_rx_hdr_dat_reset_export     : out std_logic;                                        -- export
+            reg_dp_offload_rx_hdr_dat_clk_export       : out std_logic;                                        -- export
+            reg_dp_offload_rx_hdr_dat_address_export   : out std_logic_vector(7 downto 0);                     -- export
+            reg_dp_offload_rx_hdr_dat_write_export     : out std_logic;                                        -- export
+            reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_rx_hdr_dat_read_export      : out std_logic;                                        -- export
+            reg_dp_offload_rx_hdr_dat_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dp_offload_tx_hdr_ovr_reset_export     : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_ovr_clk_export       : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_ovr_address_export   : out std_logic_vector(6 downto 0);                     -- export
+            reg_dp_offload_tx_hdr_ovr_write_export     : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0);                    -- export
+            reg_dp_offload_tx_hdr_ovr_read_export      : out std_logic;                                        -- export
+            reg_dp_offload_tx_hdr_ovr_readdata_export  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_data_buffer_reset_export         : out std_logic;                                        -- export
+            reg_diag_data_buffer_clk_export           : out std_logic;                                        -- export
+            reg_diag_data_buffer_address_export       : out std_logic_vector(4 downto 0);                     -- export
+            reg_diag_data_buffer_write_export         : out std_logic;                                        -- export
+            reg_diag_data_buffer_writedata_export     : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_data_buffer_read_export          : out std_logic;                                        -- export
+            reg_diag_data_buffer_readdata_export      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_data_buffer_clk_export           : out std_logic;                                        -- export
+            ram_diag_data_buffer_reset_export         : out std_logic;                                        -- export
+            ram_diag_data_buffer_address_export       : out std_logic_vector(13 downto 0);                    -- export
+            ram_diag_data_buffer_write_export         : out std_logic;                                        -- export
+            ram_diag_data_buffer_writedata_export     : out std_logic_vector(31 downto 0);                    -- export
+            ram_diag_data_buffer_read_export          : out std_logic;                                        -- export
+            ram_diag_data_buffer_readdata_export      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_bg_reset_export                  : out std_logic;                                        -- export
+            reg_diag_bg_clk_export                    : out std_logic;                                        -- export
+            reg_diag_bg_address_export                : out std_logic_vector(2 downto 0);                     -- export
+            reg_diag_bg_write_export                  : out std_logic;                                        -- export
+            reg_diag_bg_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_bg_read_export                   : out std_logic;                                        -- export
+            reg_diag_bg_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_bg_reset_export                  : out std_logic;                                        -- export
+            ram_diag_bg_clk_export                    : out std_logic;                                        -- export
+            ram_diag_bg_address_export                : out std_logic_vector(11 downto 0);                    -- export
+            ram_diag_bg_write_export                  : out std_logic;                                        -- export
+            ram_diag_bg_writedata_export              : out std_logic_vector(31 downto 0);                    -- export
+            ram_diag_bg_read_export                   : out std_logic;                                        -- export
+            ram_diag_bg_readdata_export               : in  std_logic_vector(31 downto 0) := (others => 'X')  -- export
         );    
     END COMPONENT qsys_unb2_test;
 

boards/uniboard2/libraries/unb2_board/hdllib.cfg

@@ -24,6 +24,10 @@ synth_files =
     src/vhdl/mms_unb2_board_sens.vhd
     src/vhdl/unb2_board_wdi_reg.vhd
     src/vhdl/ctrl_unb2_board.vhd
+    src/vhdl/unb2_board_front_io.vhd
+    src/vhdl/unb2_board_back_io.vhd
+    src/vhdl/unb2_board_ring_io.vhd
+    src/vhdl/unb2_board_10gbe.vhd
     src/vhdl/unb2_board_peripherals_pkg.vhd
     
 test_bench_files = 

boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc

@@ -26,8 +26,14 @@ create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK
 #create_clock -name {ETH_CLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {ETH_CLK}]
 create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports {ETH_CLK}]
 
-create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
-create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+#create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
+#create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+
+# from Jonathan:
+create_clock -period 1.552 -name {SA_CLK} { SA_CLK }
+create_clock -period 1.552 -name {SB_CLK} { SB_CLK }
+
+
 
 derive_pll_clocks
 
@@ -48,3 +54,7 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk200]
 set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
 set_clock_groups -asynchronous -group [get_clocks pll_clk400]
 
+# from Jonathan:
+set_false_path -from [get_clocks {*cpulse_out_bus[0]}] -to [get_clocks {*wys|clk_divtx_user}]
+set_false_path -from [get_clocks {*wys|clk_divtx_user}] -to [get_clocks {*cpulse_out_bus[0]}]
+

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -24,7 +24,7 @@
 --   . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
 --   . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
 
-LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib;
+LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -104,9 +104,7 @@ ENTITY ctrl_unb2_board IS
     ----------------------------------------------------------------------------
     g_fpga_temp_high : NATURAL := 85;
     g_app_led_red    : BOOLEAN := FALSE;  -- when TRUE use external LED control via app_led_red
-    g_dbg_led_red    : BOOLEAN := FALSE;  -- [when g_app_led_red=FALSE]: when TRUE connect pout_debug_wave to the LEDs; otherwise let ctrl_unb2_board toggle them
     g_app_led_green  : BOOLEAN := FALSE;  -- when TRUE use external LED control via app_led_green
-    g_dbg_led_green  : BOOLEAN := FALSE;  -- [when g_app_led_green=FALSE]: when TRUE connect pout_debug_wave to the LEDs; otherwise let ctrl_unb2_board toggle them
     
     g_aux            : t_c_unb2_board_aux := c_unb2_board_aux
   );
@@ -116,7 +114,7 @@ ENTITY ctrl_unb2_board IS
     --
     -- System
     cs_sim                 : OUT STD_LOGIC;
-    xo_ethclk              : OUT STD_LOGIC;   -- 25 MHz ETH_clk
+    xo_ethclk              : OUT STD_LOGIC;   -- 25 MHz ETH_CLK
     xo_rst                 : OUT STD_LOGIC;
     xo_rst_n               : OUT STD_LOGIC; 
    
@@ -136,10 +134,7 @@ ENTITY ctrl_unb2_board IS
     app_led_green          : IN STD_LOGIC := '1';
     
     -- PIOs
-    pout_debug_wave        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=> '0');
     pout_wdi               : IN  STD_LOGIC;                              -- Toggled by unb_osy; can be overriden by reg_wdi.
-    pin_system_info        : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-    pin_pps                : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- for new designs best use reg_ppsh_mosi/miso
 
     -- Manual WDI override
     reg_wdi_mosi           : IN  t_mem_mosi := c_mem_mosi_rst;
@@ -211,11 +206,11 @@ ENTITY ctrl_unb2_board IS
     TESTIO                 : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
     
     -- I2C Interface to Sensors
-    sens_sc                : INOUT STD_LOGIC := '1';
-    sens_sd                : INOUT STD_LOGIC := '1';
+    SENS_SC                : INOUT STD_LOGIC := '1';
+    SENS_SD                : INOUT STD_LOGIC := '1';
     
     -- 1GbE Control Interface
-    ETH_clk                : IN    STD_LOGIC;
+    ETH_CLK                : IN    STD_LOGIC;
     ETH_SGIN               : IN    STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
     ETH_SGOUT              : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
   );
@@ -288,7 +283,7 @@ BEGIN
   TESTIO <= (OTHERS=>'Z');  -- Leave unused INOUT tri-state
  
   -- Clock and reset
-  i_xo_ethclk <= ETH_clk;    -- use the ETH_clk pin as xo_clk
+  i_xo_ethclk <= ETH_CLK;    -- use the ETH_CLK pin as xo_clk
   ext_clk200  <= CLK;        -- use the external 200 MHz CLK as ext_clk
   ext_pps     <= PPS;        -- use more special name for PPS pin signal to ease searching for it in editor
   
@@ -389,8 +384,6 @@ BEGIN
     hw_version  => VERSION,
     id          => ID,
 
-    info        => pin_system_info,
-
     reg_mosi    => reg_unb_system_info_mosi, 
     reg_miso    => reg_unb_system_info_miso,
 
@@ -412,14 +405,8 @@ BEGIN
   END GENERATE;
 
   no_app_led_red: IF g_app_led_red = FALSE GENERATE
-    gen_dbg_led_red: IF g_dbg_led_red = TRUE GENERATE
-      TESTIO(c_unb2_board_testio_led_red)   <= pout_debug_wave(pout_debug_wave'HIGH); -- [31]   
-    END GENERATE;
-
-    gen_toggle_led_red: IF g_dbg_led_red = FALSE GENERATE
     TESTIO(c_unb2_board_testio_led_red)   <= led_toggle_red;   
   END GENERATE;
-  END GENERATE;
 
 
   -----------------------------------------------------------------------------
@@ -432,21 +419,15 @@ BEGIN
   END GENERATE;
 
   no_app_led_green: IF g_app_led_green = FALSE GENERATE
-    gen_dbg_led_green: IF g_dbg_led_green = TRUE GENERATE
-      TESTIO(c_unb2_board_testio_led_green) <= pout_debug_wave(pout_debug_wave'HIGH-1); -- [30]
-    END GENERATE;
-
-    gen_toggle_led_green: IF g_dbg_led_green = FALSE GENERATE
     TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;   
   END GENERATE;
-  END GENERATE;
 
 
   ------------------------------------------------------------------------------
   -- Toggle red LED when unb2_minimal is running, green LED for other designs.
   ------------------------------------------------------------------------------
-  led_toggle_red <= sel_a_b(g_design_name(1 TO 12)="unb2_minimal", led_toggle, '0');
-  led_toggle_green <= sel_a_b(g_design_name(1 TO 12)/="unb2_minimal", led_toggle, '0');
+  led_toggle_red <= sel_a_b(g_design_name(1 TO 8)="unb2_min", led_toggle, '0');
+  led_toggle_green <= sel_a_b(g_design_name(1 TO 8)/="unb2_min", led_toggle, '0');
 
   u_toggle : ENTITY common_lib.common_toggle
   PORT MAP (
@@ -546,9 +527,6 @@ BEGIN
     reg_mosi         => reg_ppsh_mosi,
     reg_miso         => reg_ppsh_miso,
     
-    -- Old PIO support (for backwards compatibility with pin_pps on ctrl_unb2_board)
-    pin_pps          => pin_pps,
-    
     -- Streaming clock domain
     pps_sys          => dp_pps
   );
@@ -577,8 +555,8 @@ BEGIN
     reg_miso  => reg_unb_sens_miso,
     
     -- i2c bus
-    scl       => sens_sc,
-    sda       => sens_sd,
+    scl       => SENS_SC,
+    sda       => SENS_SD,
 
     -- Temperature alarm
     temp_alarm => temp_alarm

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_10gbe_front_and_ring IS
+  GENERIC (
+    g_technology     : NATURAL := c_tech_arria10;
+    g_sim            : BOOLEAN := FALSE;
+    g_sim_level              : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
+    g_nof_macs               : NATURAL;
+    g_tx_fifo_fill           : NATURAL := 10;    -- Release tx packet only when sufficiently data is available, 
+    g_tx_fifo_size           : NATURAL := 256;   -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+    g_rx_fifo_size           : NATURAL := 256;   -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+    g_word_alignment_padding : BOOLEAN := FALSE
+  );
+  PORT (
+    tr_ref_clk          : IN  STD_LOGIC := '0';
+
+    -- MM interface
+    mm_rst              : IN  STD_LOGIC;
+    mm_clk              : IN  STD_LOGIC;
+
+    reg_mac_mosi        : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_mac_miso        : OUT t_mem_miso;
+
+    -- DP interface
+    dp_rst              : IN  STD_LOGIC := '0';
+    dp_clk              : IN  STD_LOGIC := '0';
+
+    snk_out_arr         : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+    snk_in_arr          : IN  t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+
+    src_in_arr          : IN  t_dp_siso_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+    src_out_arr         : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+
+    -- Serial IO
+    serial_tx_arr       : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0);
+    serial_rx_arr       : IN  STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0')
+  );
+END unb2_board_10gbe_front_and_ring;
+
+
+ARCHITECTURE str OF unb2_board_10gbe_front_and_ring IS
+
+  SIGNAL tr_ref_clk_312 : STD_LOGIC;
+  SIGNAL tr_ref_clk_156 : STD_LOGIC;
+  SIGNAL tr_ref_rst_156 : STD_LOGIC;
+
+BEGIN
+  u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+  GENERIC MAP (
+    g_technology => g_technology
+  )
+  PORT MAP (
+    refclk_644 => tr_ref_clk,
+    rst_in     => mm_rst,
+    clk_156    => tr_ref_clk_156,
+    clk_312    => tr_ref_clk_312,
+    rst_156    => tr_ref_rst_156,
+    rst_312    => OPEN
+  );
+
+
+  u_tr_10GbE_front_and_ring: ENTITY tr_10GbE_lib.tr_10GbE
+    GENERIC MAP (
+      g_technology    => g_technology,
+      g_sim           => g_sim,
+      g_sim_level     => 1,
+      g_nof_macs      => g_nof_macs,
+      g_tx_fifo_fill  => g_tx_fifo_fill,
+      g_tx_fifo_size  => g_tx_fifo_size
+    )
+    PORT MAP (
+      -- Transceiver PLL reference clock
+      tr_ref_clk_644      => tr_ref_clk,
+      tr_ref_clk_312      => tr_ref_clk_312,  -- 312.5      MHz for 10GBASE-R
+      tr_ref_clk_156      => tr_ref_clk_156,  -- 156.25     MHz for 10GBASE-R or for XAUI
+      tr_ref_rst_156      => tr_ref_rst_156,  --                for 10GBASE-R or for XAUI
+
+      -- MM interface
+      mm_rst              => mm_rst,
+      mm_clk              => mm_clk,
+
+      reg_mac_mosi        => reg_mac_mosi,
+      reg_mac_miso        => reg_mac_miso,
+
+      -- DP interface
+      dp_rst              => dp_rst,
+      dp_clk              => dp_clk,
+
+      src_out_arr         => src_out_arr,
+      src_in_arr          => src_in_arr,
+
+      snk_out_arr         => snk_out_arr,
+      snk_in_arr          => snk_in_arr,
+
+      -- Serial IO
+      serial_tx_arr       => serial_tx_arr,
+      serial_rx_arr       => serial_rx_arr
+    );
+ 
+END str;

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_back_io IS
+  PORT (
+    serial_tx_arr  : IN  STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+    serial_rx_arr  : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+
+    -- back transceivers
+    BCK_RX       : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+    BCK_TX       : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+
+    BCK_SDA      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+    BCK_SCL      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+    BCK_ERR      : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0)
+  );
+END unb2_board_back_io;
+
+ARCHITECTURE str OF unb2_board_back_io IS
+
+  -- help signals so we can iterate through buses
+  SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+  connect_back : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
+    BCK_TX(i)    <=  si_tx_arr(i);
+    si_rx_arr(i) <=  BCK_RX(i);
+  END GENERATE;
+
+
+  wire_signals : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
+    si_tx_arr(i) <= serial_tx_arr(i);
+    serial_rx_arr(i)  <= si_rx_arr(i);
+  END GENERATE;
+
+END;

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_front_io IS
+  PORT (
+    serial_tx_arr  : IN  STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+    serial_rx_arr  : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+
+    QSFP_0_RX    : IN    STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+    QSFP_0_TX    : OUT   STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_2_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_2_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_3_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_3_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_4_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_4_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_5_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+--    QSFP_5_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+    QSFP_SDA     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+    QSFP_SCL     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+    QSFP_RST     : INOUT STD_LOGIC;
+
+    QSFP_LED     : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+  );
+END unb2_board_front_io;
+
+ARCHITECTURE str OF unb2_board_front_io IS
+
+  -- help signals so we can iterate through buses
+  SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+  QSFP_0_TX(0)    <=  si_tx_arr(0);
+ -- QSFP_0_TX(1)    <=  si_tx_arr(1);
+ -- QSFP_0_TX(2)    <=  si_tx_arr(2);
+ -- QSFP_0_TX(3)    <=  si_tx_arr(3);
+
+ -- QSFP_1_TX(0)    <=  si_tx_arr(4);
+ -- QSFP_1_TX(1)    <=  si_tx_arr(5);
+ -- QSFP_1_TX(2)    <=  si_tx_arr(6);
+ -- QSFP_1_TX(3)    <=  si_tx_arr(7);
+
+ -- QSFP_2_TX(0)    <=  si_tx_arr(8);
+ -- QSFP_2_TX(1)    <=  si_tx_arr(9);
+ -- QSFP_2_TX(2)    <=  si_tx_arr(10);
+ -- QSFP_2_TX(3)    <=  si_tx_arr(11);
+
+ -- QSFP_3_TX(0)    <=  si_tx_arr(12);
+ -- QSFP_3_TX(1)    <=  si_tx_arr(13);
+ -- QSFP_3_TX(2)    <=  si_tx_arr(14);
+ -- QSFP_3_TX(3)    <=  si_tx_arr(15);
+
+ -- QSFP_4_TX(0)    <=  si_tx_arr(16);
+ -- QSFP_4_TX(1)    <=  si_tx_arr(17);
+ -- QSFP_4_TX(2)    <=  si_tx_arr(18);
+ -- QSFP_4_TX(3)    <=  si_tx_arr(19);
+
+ -- QSFP_5_TX(0)    <=  si_tx_arr(20);
+ -- QSFP_5_TX(1)    <=  si_tx_arr(21);
+ -- QSFP_5_TX(2)    <=  si_tx_arr(22);
+ -- QSFP_5_TX(3)    <=  si_tx_arr(23);
+
+
+  si_rx_arr(0)    <=  QSFP_0_RX(0);
+  --si_rx_arr(1)    <=  QSFP_0_RX(1);
+  --si_rx_arr(2)    <=  QSFP_0_RX(2);
+  --si_rx_arr(3)    <=  QSFP_0_RX(3);
+
+  --si_rx_arr(4)    <=  QSFP_1_RX(0);
+  --si_rx_arr(5)    <=  QSFP_1_RX(1);
+  --si_rx_arr(6)    <=  QSFP_1_RX(2);
+  --si_rx_arr(7)    <=  QSFP_1_RX(3);
+
+  --si_rx_arr(8)    <=  QSFP_2_RX(0);
+  --si_rx_arr(9)    <=  QSFP_2_RX(1);
+  --si_rx_arr(10)   <=  QSFP_2_RX(2);
+  --si_rx_arr(11)   <=  QSFP_2_RX(3);
+
+  --si_rx_arr(12)   <=  QSFP_3_RX(0);
+  --si_rx_arr(13)   <=  QSFP_3_RX(1);
+  --si_rx_arr(14)   <=  QSFP_3_RX(2);
+  --si_rx_arr(15)   <=  QSFP_3_RX(3);
+
+  --si_rx_arr(16)   <=  QSFP_4_RX(0);
+  --si_rx_arr(17)   <=  QSFP_4_RX(1);
+  --si_rx_arr(18)   <=  QSFP_4_RX(2);
+  --si_rx_arr(19)   <=  QSFP_4_RX(3);
+
+  --si_rx_arr(20)   <=  QSFP_5_RX(0);
+  --si_rx_arr(21)   <=  QSFP_5_RX(1);
+  --si_rx_arr(22)   <=  QSFP_5_RX(2);
+  --si_rx_arr(23)   <=  QSFP_5_RX(3);
+
+
+  wire_signals : FOR i IN 0 TO c_unb2_board_tr_qsfp_hw_nof_lines-1 GENERATE
+    si_tx_arr(i) <= serial_tx_arr(i);
+    serial_rx_arr(i)  <= si_rx_arr(i);
+  END GENERATE;
+
+END;

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd

@@ -64,6 +64,29 @@ PACKAGE unb2_board_pkg IS
   CONSTANT c_unb2_board_signature_eth1g       : INTEGER := TO_SINT(c_unb2_board_signature_eth1g_slv  );
   CONSTANT c_unb2_board_signature_eth10g      : INTEGER := TO_SINT(c_unb2_board_signature_eth10g_slv );
   
+  -- Transceivers
+  TYPE t_c_unb2_board_tr IS RECORD
+    nof_bus                           : NATURAL;
+    bus_w                             : NATURAL;
+    i2c_w                             : NATURAL;
+  END RECORD;
+
+  CONSTANT c_unb2_board_tr_back              : t_c_unb2_board_tr := (1, 48, 3); -- per node: 1 bus with 48 channels
+  CONSTANT c_unb2_board_tr_ring              : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+  CONSTANT c_unb2_board_tr_qsfp              : t_c_unb2_board_tr := (6, 4,  6); -- per node: 6 buses with 4 channels
+  CONSTANT c_unb2_board_tr_qsfp_nof_leds     : NATURAL := 12;
+
+  -- Transceivers network array types for the UniBoard mesh HW and for a backplane HW
+  CONSTANT c_unb2_board_tr_back_hw_nof_bus   : NATURAL := 1;
+  CONSTANT c_unb2_board_tr_back_hw_bus_w     : NATURAL := 48;
+  CONSTANT c_unb2_board_tr_ring_hw_nof_bus   : NATURAL := 2;
+  CONSTANT c_unb2_board_tr_ring_hw_bus_w     : NATURAL := 12;
+  CONSTANT c_unb2_board_tr_qsfp_hw_nof_bus   : NATURAL := 6;
+  CONSTANT c_unb2_board_tr_qsfp_hw_bus_w     : NATURAL := 4;
+
+  CONSTANT c_unb2_board_tr_qsfp_hw_nof_lines : NATURAL := (c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w);
+  CONSTANT c_unb2_board_tr_back_hw_nof_lines : NATURAL := (c_unb2_board_tr_back.nof_bus * c_unb2_board_tr_back.bus_w);
+  CONSTANT c_unb2_board_tr_ring_hw_nof_lines : NATURAL := (c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w);
 
   -- Auxiliary
   
@@ -93,15 +116,6 @@ PACKAGE unb2_board_pkg IS
   
   TYPE t_e_unb2_board_node IS (e_any);
 
-  -- UniBoard Common Interface
-  TYPE t_c_unb2_board_ci IS RECORD
-    aux                               : t_c_unb2_board_aux;
-  END RECORD;
-  
-  -- FIXME: this does not compile in modelsim: (pls compare with unb1_board_pkg.vhd)
-  --CONSTANT c_unb2_board_ci            : t_c_unb2_board_ci := (c_unb2_board_aux);
-
-  
   TYPE t_unb2_board_fw_version IS RECORD
     hi                                : NATURAL;  -- = 0..15
     lo                                : NATURAL;  -- = 0..15, firmware version is: hi.lo

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_ring_io IS
+  PORT (
+    serial_tx_arr  : IN  STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+    serial_rx_arr  : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+
+    -- ring transceivers
+    RING_0_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+    RING_0_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+    RING_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+    RING_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0)
+  );
+END unb2_board_ring_io;
+
+ARCHITECTURE str OF unb2_board_ring_io IS
+
+  -- help signals so we can iterate through buses
+  SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+  RING_0_TX(0)    <=  si_tx_arr(0);
+  RING_0_TX(1)    <=  si_tx_arr(1);
+  RING_0_TX(2)    <=  si_tx_arr(2);
+  RING_0_TX(3)    <=  si_tx_arr(3);
+  RING_0_TX(4)    <=  si_tx_arr(4);
+  RING_0_TX(5)    <=  si_tx_arr(5);
+  RING_0_TX(6)    <=  si_tx_arr(6);
+  RING_0_TX(7)    <=  si_tx_arr(7);
+  RING_0_TX(8)    <=  si_tx_arr(8);
+  RING_0_TX(9)    <=  si_tx_arr(9);
+  RING_0_TX(10)   <=  si_tx_arr(10);
+  RING_0_TX(11)   <=  si_tx_arr(11);
+
+  RING_1_TX(0)    <=  si_tx_arr(12);
+  RING_1_TX(1)    <=  si_tx_arr(13);
+  RING_1_TX(2)    <=  si_tx_arr(14);
+  RING_1_TX(3)    <=  si_tx_arr(15);
+  RING_1_TX(4)    <=  si_tx_arr(16);
+  RING_1_TX(5)    <=  si_tx_arr(17);
+  RING_1_TX(6)    <=  si_tx_arr(18);
+  RING_1_TX(7)    <=  si_tx_arr(19);
+  RING_1_TX(8)    <=  si_tx_arr(20);
+  RING_1_TX(9)    <=  si_tx_arr(21);
+  RING_1_TX(10)   <=  si_tx_arr(22);
+  RING_1_TX(11)   <=  si_tx_arr(23);
+
+
+  si_rx_arr(0)    <=  RING_0_RX(0);
+  si_rx_arr(1)    <=  RING_0_RX(1);
+  si_rx_arr(2)    <=  RING_0_RX(2);
+  si_rx_arr(3)    <=  RING_0_RX(3);
+  si_rx_arr(4)    <=  RING_0_RX(4);
+  si_rx_arr(5)    <=  RING_0_RX(5);
+  si_rx_arr(6)    <=  RING_0_RX(6);
+  si_rx_arr(7)    <=  RING_0_RX(7);
+  si_rx_arr(8)    <=  RING_0_RX(8);
+  si_rx_arr(9)    <=  RING_0_RX(9);
+  si_rx_arr(10)   <=  RING_0_RX(10);
+  si_rx_arr(11)   <=  RING_0_RX(11);
+
+  si_rx_arr(12)    <=  RING_1_RX(0);
+  si_rx_arr(13)    <=  RING_1_RX(1);
+  si_rx_arr(14)    <=  RING_1_RX(2);
+  si_rx_arr(15)    <=  RING_1_RX(3);
+  si_rx_arr(16)    <=  RING_1_RX(4);
+  si_rx_arr(17)    <=  RING_1_RX(5);
+  si_rx_arr(18)    <=  RING_1_RX(6);
+  si_rx_arr(19)    <=  RING_1_RX(7);
+  si_rx_arr(20)    <=  RING_1_RX(8);
+  si_rx_arr(21)    <=  RING_1_RX(9);
+  si_rx_arr(22)   <=  RING_1_RX(10);
+  si_rx_arr(23)   <=  RING_1_RX(11);
+
+
+  wire_signals : FOR i IN 0 TO c_unb2_board_tr_ring_hw_nof_lines-1 GENERATE
+    si_tx_arr(i) <= serial_tx_arr(i);
+    serial_rx_arr(i)  <= si_rx_arr(i);
+  END GENERATE;
+
+END;