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Commit 97dbde25 authored by Eric Kooistra's avatar Eric Kooistra
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reset output pulses

parent 8f6013ff
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......@@ -60,9 +60,9 @@ ARCHITECTURE str OF common_pulser_us_ms_s IS
BEGIN
-- register output pulses to ease timing closure
pulse_us <= i_pulse_us WHEN rising_edge(clk);
pulse_ms <= i_pulse_ms WHEN rising_edge(clk);
pulse_s <= i_pulse_s WHEN rising_edge(clk);
pulse_us <= '0' WHEN rst='1' ELSE i_pulse_us WHEN rising_edge(clk);
pulse_ms <= '0' WHEN rst='1' ELSE i_pulse_ms WHEN rising_edge(clk);
pulse_s <= '0' WHEN rst='1' ELSE i_pulse_s WHEN rising_edge(clk);
p_clk : PROCESS(clk)
BEGIN
......
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