diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
index 6344711e592e77184d4aab9ba56863eda47c2800..8c70cfcd1934e45a338704718a092c00e18622cb 100644
--- a/boards/uniboard2/designs/unb2_test/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -1,8 +1,11 @@
hdl_lib_name = unb2_test
hdl_library_clause_name = unb2_test_lib
-hdl_lib_uses = common mm unb2_board
+#hdl_lib_uses = common mm unb2_board
+hdl_lib_uses = common technology mm unb2_board dp eth tech_tse tr_10GbE diagnostics diag
hdl_lib_technology = ip_arria10
+
+
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
@@ -18,6 +21,15 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb2_test.qsys .
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_128_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_32_2.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_0.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_1.hex ../..
+ $UNB/Firmware/designs/unb_dp_offload/src/hex/counter_data_64_2.hex ../..
quartus_qsf_files =
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index 2e366698b3d6581a2c1e7e1dce2e38a168ef2fb6..b05c82b799a5ea519ba1d51ce2e2668a9a4bba22 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -21,7 +21,7 @@
{
datum _sortIndex
{
- value = "7";
+ value = "6";
type = "int";
}
}
@@ -29,7 +29,7 @@
{
datum baseAddress
{
- value = "8192";
+ value = "32768";
type = "String";
}
}
@@ -37,7 +37,7 @@
{
datum baseAddress
{
- value = "128";
+ value = "12352";
type = "String";
}
}
@@ -45,7 +45,7 @@
{
datum baseAddress
{
- value = "16384";
+ value = "8192";
type = "String";
}
}
@@ -77,7 +77,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "3";
type = "int";
}
}
@@ -85,7 +85,7 @@
{
datum baseAddress
{
- value = "392";
+ value = "12608";
type = "String";
}
}
@@ -101,7 +101,7 @@
{
datum _sortIndex
{
- value = "3";
+ value = "2";
type = "int";
}
}
@@ -118,67 +118,203 @@
type = "String";
}
}
- element pio_debug_wave
+ element pio_pps
{
datum _sortIndex
{
- value = "2";
+ value = "10";
type = "int";
}
}
- element pio_debug_wave.s1
+ element pio_pps.mem
{
datum baseAddress
{
- value = "320";
+ value = "12600";
type = "String";
}
}
- element pio_pps
+ element pio_system_info
{
datum _sortIndex
{
- value = "11";
+ value = "9";
type = "int";
}
}
- element pio_pps.mem
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element pio_wdi.s1
{
datum baseAddress
{
- value = "384";
+ value = "12304";
type = "String";
}
}
- element pio_system_info
+ element qsys_unb2_test
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element ram_diag_bg
{
datum _sortIndex
{
- value = "10";
+ value = "27";
type = "int";
}
}
- element pio_system_info.mem
+ element ram_diag_bg.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "16384";
+ type = "String";
}
}
- element pio_wdi
+ element ram_diag_data_buffer
{
datum _sortIndex
{
- value = "5";
+ value = "25";
type = "int";
}
}
- element pio_wdi.s1
+ element ram_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "65536";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "String";
+ }
+ }
+ element reg_diag_bg
+ {
+ datum _sortIndex
+ {
+ value = "26";
+ type = "int";
+ }
+ }
+ element reg_diag_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_diag_data_buffer
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "String";
+ }
+ }
+ element reg_dp_offload_tx
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "12448";
+ type = "String";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "13312";
+ type = "String";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr.mem
{
datum baseAddress
{
- value = "336";
+ value = "512";
type = "String";
}
}
@@ -186,7 +322,7 @@
{
datum _sortIndex
{
- value = "15";
+ value = "14";
type = "int";
}
}
@@ -194,7 +330,7 @@
{
datum baseAddress
{
- value = "376";
+ value = "12592";
type = "String";
}
}
@@ -202,7 +338,7 @@
{
datum _sortIndex
{
- value = "16";
+ value = "15";
type = "int";
}
}
@@ -210,7 +346,7 @@
{
datum baseAddress
{
- value = "368";
+ value = "12584";
type = "String";
}
}
@@ -218,7 +354,7 @@
{
datum _sortIndex
{
- value = "14";
+ value = "13";
type = "int";
}
}
@@ -226,7 +362,7 @@
{
datum baseAddress
{
- value = "192";
+ value = "12480";
type = "String";
}
}
@@ -234,7 +370,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "16";
type = "int";
}
}
@@ -242,7 +378,7 @@
{
datum baseAddress
{
- value = "360";
+ value = "12576";
type = "String";
}
}
@@ -250,7 +386,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "17";
type = "int";
}
}
@@ -258,7 +394,7 @@
{
datum baseAddress
{
- value = "352";
+ value = "12296";
type = "String";
}
}
@@ -266,7 +402,7 @@
{
datum _sortIndex
{
- value = "13";
+ value = "12";
type = "int";
}
}
@@ -274,7 +410,23 @@
{
datum baseAddress
{
- value = "224";
+ value = "12512";
+ type = "String";
+ }
+ }
+ element reg_tr_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE.mem
+ {
+ datum baseAddress
+ {
+ value = "262144";
type = "String";
}
}
@@ -282,7 +434,7 @@
{
datum _sortIndex
{
- value = "8";
+ value = "7";
type = "int";
}
}
@@ -290,7 +442,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "12544";
type = "String";
}
}
@@ -298,7 +450,7 @@
{
datum _sortIndex
{
- value = "12";
+ value = "11";
type = "int";
}
}
@@ -319,7 +471,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "8";
type = "int";
}
}
@@ -340,7 +492,7 @@
{
datum _sortIndex
{
- value = "6";
+ value = "5";
type = "int";
}
}
@@ -348,7 +500,7 @@
{
datum baseAddress
{
- value = "288";
+ value = "12320";
type = "String";
}
}
@@ -365,7 +517,7 @@
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="unb2_minimal.qpf" />
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
@@ -468,11 +620,6 @@
type="conduit"
dir="end" />
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface
- name="pio_debug_wave_external_connection"
- internal="pio_debug_wave.external_connection"
- type="conduit"
- dir="end" />
<interface
name="pio_pps_address"
internal="pio_pps.address"
@@ -541,195 +688,510 @@
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_address"
- internal="reg_dpmm_ctrl.address"
+ name="ram_diag_bg_address"
+ internal="ram_diag_bg.address"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_clk"
- internal="reg_dpmm_ctrl.clk"
+ name="ram_diag_bg_clk"
+ internal="ram_diag_bg.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_read"
- internal="reg_dpmm_ctrl.read"
+ name="ram_diag_bg_read"
+ internal="ram_diag_bg.read"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_readdata"
- internal="reg_dpmm_ctrl.readdata"
+ name="ram_diag_bg_readdata"
+ internal="ram_diag_bg.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_reset"
- internal="reg_dpmm_ctrl.reset"
+ name="ram_diag_bg_reset"
+ internal="ram_diag_bg.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_write"
- internal="reg_dpmm_ctrl.write"
+ name="ram_diag_bg_write"
+ internal="ram_diag_bg.write"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_ctrl_writedata"
- internal="reg_dpmm_ctrl.writedata"
+ name="ram_diag_bg_writedata"
+ internal="ram_diag_bg.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_address"
- internal="reg_dpmm_data.address"
+ name="ram_diag_data_buffer_address"
+ internal="ram_diag_data_buffer.address"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_clk"
- internal="reg_dpmm_data.clk"
+ name="ram_diag_data_buffer_clk"
+ internal="ram_diag_data_buffer.clk"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_read"
- internal="reg_dpmm_data.read"
+ name="ram_diag_data_buffer_read"
+ internal="ram_diag_data_buffer.read"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_readdata"
- internal="reg_dpmm_data.readdata"
+ name="ram_diag_data_buffer_readdata"
+ internal="ram_diag_data_buffer.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_reset"
- internal="reg_dpmm_data.reset"
+ name="ram_diag_data_buffer_reset"
+ internal="ram_diag_data_buffer.reset"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_write"
- internal="reg_dpmm_data.write"
+ name="ram_diag_data_buffer_write"
+ internal="ram_diag_data_buffer.write"
type="conduit"
dir="end" />
<interface
- name="reg_dpmm_data_writedata"
- internal="reg_dpmm_data.writedata"
+ name="ram_diag_data_buffer_writedata"
+ internal="ram_diag_data_buffer.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_address"
- internal="reg_epcs.address"
+ name="reg_bsn_monitor_address"
+ internal="reg_bsn_monitor.address"
type="conduit"
dir="end" />
- <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
<interface
- name="reg_epcs_read"
- internal="reg_epcs.read"
+ name="reg_bsn_monitor_clk"
+ internal="reg_bsn_monitor.clk"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_readdata"
- internal="reg_epcs.readdata"
+ name="reg_bsn_monitor_read"
+ internal="reg_bsn_monitor.read"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_reset"
- internal="reg_epcs.reset"
+ name="reg_bsn_monitor_readdata"
+ internal="reg_bsn_monitor.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_write"
- internal="reg_epcs.write"
+ name="reg_bsn_monitor_reset"
+ internal="reg_bsn_monitor.reset"
type="conduit"
dir="end" />
<interface
- name="reg_epcs_writedata"
- internal="reg_epcs.writedata"
+ name="reg_bsn_monitor_write"
+ internal="reg_bsn_monitor.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_address"
- internal="reg_mmdp_ctrl.address"
+ name="reg_bsn_monitor_writedata"
+ internal="reg_bsn_monitor.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_clk"
- internal="reg_mmdp_ctrl.clk"
+ name="reg_diag_bg_address"
+ internal="reg_diag_bg.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_read"
- internal="reg_mmdp_ctrl.read"
+ name="reg_diag_bg_clk"
+ internal="reg_diag_bg.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_readdata"
- internal="reg_mmdp_ctrl.readdata"
+ name="reg_diag_bg_read"
+ internal="reg_diag_bg.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_reset"
- internal="reg_mmdp_ctrl.reset"
+ name="reg_diag_bg_readdata"
+ internal="reg_diag_bg.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_write"
- internal="reg_mmdp_ctrl.write"
+ name="reg_diag_bg_reset"
+ internal="reg_diag_bg.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_ctrl_writedata"
- internal="reg_mmdp_ctrl.writedata"
+ name="reg_diag_bg_write"
+ internal="reg_diag_bg.write"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_address"
- internal="reg_mmdp_data.address"
+ name="reg_diag_bg_writedata"
+ internal="reg_diag_bg.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_clk"
- internal="reg_mmdp_data.clk"
+ name="reg_diag_data_buffer_address"
+ internal="reg_diag_data_buffer.address"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_read"
- internal="reg_mmdp_data.read"
+ name="reg_diag_data_buffer_clk"
+ internal="reg_diag_data_buffer.clk"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_readdata"
- internal="reg_mmdp_data.readdata"
+ name="reg_diag_data_buffer_read"
+ internal="reg_diag_data_buffer.read"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_reset"
- internal="reg_mmdp_data.reset"
+ name="reg_diag_data_buffer_readdata"
+ internal="reg_diag_data_buffer.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_write"
- internal="reg_mmdp_data.write"
+ name="reg_diag_data_buffer_reset"
+ internal="reg_diag_data_buffer.reset"
type="conduit"
dir="end" />
<interface
- name="reg_mmdp_data_writedata"
- internal="reg_mmdp_data.writedata"
+ name="reg_diag_data_buffer_write"
+ internal="reg_diag_data_buffer.write"
type="conduit"
dir="end" />
<interface
- name="reg_remu_address"
- internal="reg_remu.address"
+ name="reg_diag_data_buffer_writedata"
+ internal="reg_diag_data_buffer.writedata"
type="conduit"
dir="end" />
- <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
<interface
- name="reg_remu_read"
- internal="reg_remu.read"
+ name="reg_dp_offload_rx_hdr_dat_address"
+ internal="reg_dp_offload_rx_hdr_dat.address"
type="conduit"
dir="end" />
<interface
- name="reg_remu_readdata"
- internal="reg_remu.readdata"
+ name="reg_dp_offload_rx_hdr_dat_clk"
+ internal="reg_dp_offload_rx_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
- name="reg_remu_reset"
- internal="reg_remu.reset"
+ name="reg_dp_offload_rx_hdr_dat_read"
+ internal="reg_dp_offload_rx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_reset"
+ internal="reg_dp_offload_rx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_write"
+ internal="reg_dp_offload_rx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_address"
+ internal="reg_dp_offload_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_clk"
+ internal="reg_dp_offload_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_address"
+ internal="reg_dp_offload_tx_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_clk"
+ internal="reg_dp_offload_tx_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_read"
+ internal="reg_dp_offload_tx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_reset"
+ internal="reg_dp_offload_tx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_write"
+ internal="reg_dp_offload_tx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_address"
+ internal="reg_dp_offload_tx_hdr_ovr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_clk"
+ internal="reg_dp_offload_tx_hdr_ovr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_read"
+ internal="reg_dp_offload_tx_hdr_ovr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_readdata"
+ internal="reg_dp_offload_tx_hdr_ovr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_reset"
+ internal="reg_dp_offload_tx_hdr_ovr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_write"
+ internal="reg_dp_offload_tx_hdr_ovr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_writedata"
+ internal="reg_dp_offload_tx_hdr_ovr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_read"
+ internal="reg_dp_offload_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_readdata"
+ internal="reg_dp_offload_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_reset"
+ internal="reg_dp_offload_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_write"
+ internal="reg_dp_offload_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_writedata"
+ internal="reg_dp_offload_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_address"
+ internal="reg_dpmm_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_clk"
+ internal="reg_dpmm_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_read"
+ internal="reg_dpmm_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_readdata"
+ internal="reg_dpmm_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_reset"
+ internal="reg_dpmm_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_write"
+ internal="reg_dpmm_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_writedata"
+ internal="reg_dpmm_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_address"
+ internal="reg_dpmm_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_clk"
+ internal="reg_dpmm_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_read"
+ internal="reg_dpmm_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_readdata"
+ internal="reg_dpmm_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_reset"
+ internal="reg_dpmm_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_write"
+ internal="reg_dpmm_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_writedata"
+ internal="reg_dpmm_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_reset"
+ internal="reg_epcs.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_write"
+ internal="reg_epcs.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_writedata"
+ internal="reg_epcs.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_address"
+ internal="reg_remu.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_remu_read"
+ internal="reg_remu.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
type="conduit"
dir="end" />
<interface
@@ -742,6 +1204,46 @@
internal="reg_remu.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_tr_10gbe_address"
+ internal="reg_tr_10GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_clk"
+ internal="reg_tr_10GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_read"
+ internal="reg_tr_10GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_readdata"
+ internal="reg_tr_10GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_reset"
+ internal="reg_tr_10GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_waitrequest"
+ internal="reg_tr_10GbE.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_write"
+ internal="reg_tr_10GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_writedata"
+ internal="reg_tr_10GbE.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_sens_address"
internal="reg_unb_sens.address"
@@ -864,10 +1366,10 @@
<parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
- <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataAddrWidth" value="19" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_epcs.mem' start='0xC0' end='0xE0' /><slave name='reg_remu.mem' start='0xE0' end='0x100' /><slave name='reg_unb_sens.mem' start='0x100' end='0x120' /><slave name='timer_0.s1' start='0x120' end='0x140' /><slave name='pio_debug_wave.s1' start='0x140' end='0x150' /><slave name='pio_wdi.s1' start='0x150' end='0x160' /><slave name='reg_mmdp_data.mem' start='0x160' end='0x168' /><slave name='reg_mmdp_ctrl.mem' start='0x168' end='0x170' /><slave name='reg_dpmm_data.mem' start='0x170' end='0x178' /><slave name='reg_dpmm_ctrl.mem' start='0x178' end='0x180' /><slave name='pio_pps.mem' start='0x180' end='0x188' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x188' end='0x190' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_bg.mem' start='0x3080' end='0x30A0' /><slave name='reg_dp_offload_tx.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_remu.mem' start='0x30E0' end='0x3100' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3120' /><slave name='reg_mmdp_ctrl.mem' start='0x3120' end='0x3128' /><slave name='reg_dpmm_data.mem' start='0x3128' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='pio_pps.mem' start='0x3138' end='0x3140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3140' end='0x3148' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_bg.mem' start='0x4000' end='0x8000' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -1071,48 +1573,99 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
+ <module name="pio_pps" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_wdi" kind="altera_avalon_pio" version="14.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="ram_diag_bg" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="12" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="ram_diag_data_buffer"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="14" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_bsn_monitor" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_diag_bg" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_diag_data_buffer"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_dp_offload_rx_hdr_dat"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="8" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module
+ name="reg_dp_offload_tx"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module
- name="pio_debug_wave"
- kind="altera_avalon_pio"
- version="14.1"
+ name="reg_dp_offload_tx_hdr_dat"
+ kind="avs_common_mm"
+ version="1.0"
enabled="1">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="50000000" />
- <parameter name="direction" value="Output" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="32" />
- </module>
- <module name="pio_pps" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="1" />
+ <parameter name="g_adr_w" value="8" />
<parameter name="g_dat_w" value="32" />
</module>
- <module name="pio_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <module
+ name="reg_dp_offload_tx_hdr_ovr"
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="5" />
+ <parameter name="g_adr_w" value="7" />
<parameter name="g_dat_w" value="32" />
</module>
- <module name="pio_wdi" kind="altera_avalon_pio" version="14.1" enabled="1">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="50000000" />
- <parameter name="direction" value="Output" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="1" />
- </module>
<module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
@@ -1143,6 +1696,15 @@
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
</module>
+ <module
+ name="reg_tr_10GbE"
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
<module name="reg_unb_sens" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="3" />
@@ -1175,7 +1737,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0188" />
+ <parameter name="baseAddress" value="0x3140" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1193,7 +1755,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x3100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1220,7 +1782,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
+ <parameter name="baseAddress" value="0x3138" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1238,7 +1800,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00e0" />
+ <parameter name="baseAddress" value="0x30e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1247,7 +1809,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="baseAddress" value="0x30c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1256,7 +1818,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0178" />
+ <parameter name="baseAddress" value="0x3130" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1265,7 +1827,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0170" />
+ <parameter name="baseAddress" value="0x3128" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1274,7 +1836,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0168" />
+ <parameter name="baseAddress" value="0x3120" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1283,23 +1845,68 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0160" />
+ <parameter name="baseAddress" value="0x3008" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="avs_eth_0.mms_ram">
+ end="reg_tr_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x2000" />
+ <parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="avs_eth_0.mms_reg">
+ end="reg_bsn_monitor.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x30a0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3400" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_ovr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
@@ -1308,7 +1915,25 @@
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="avs_eth_0.mms_tse">
+ end="ram_diag_data_buffer.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00010000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
@@ -1317,36 +1942,54 @@
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="onchip_memory2_0.s1">
+ end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="pio_wdi.s1">
+ end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0150" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="timer_0.s1">
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0120" />
+ <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3010" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="14.1"
start="cpu_0.data_master"
- end="pio_debug_wave.s1">
+ end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0140" />
+ <parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -1367,11 +2010,6 @@
<parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
- <connection
- kind="clock"
- version="14.1"
- start="clk_0.clk"
- end="pio_debug_wave.clk" />
<connection kind="clock" version="14.1" start="clk_0.clk" end="jtag_uart_0.clk" />
<connection kind="clock" version="14.1" start="clk_0.clk" end="pio_wdi.clk" />
<connection kind="clock" version="14.1" start="clk_0.clk" end="timer_0.clk" />
@@ -1421,33 +2059,78 @@
version="14.1"
start="clk_0.clk"
end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_bsn_monitor.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_hdr_ovr.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="ram_diag_bg.system" />
<connection
kind="interrupt"
version="14.1"
start="cpu_0.irq"
end="avs_eth_0.interrupt">
- <parameter name="irqNumber" value="2" />
+ <parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="14.1"
start="cpu_0.irq"
end="jtag_uart_0.irq">
- <parameter name="irqNumber" value="0" />
+ <parameter name="irqNumber" value="1" />
</connection>
<connection kind="interrupt" version="14.1" start="cpu_0.irq" end="timer_0.irq">
- <parameter name="irqNumber" value="1" />
+ <parameter name="irqNumber" value="2" />
</connection>
<connection
kind="reset"
version="14.1"
start="clk_0.clk_reset"
end="avs_eth_0.mm_reset" />
- <connection
- kind="reset"
- version="14.1"
- start="clk_0.clk_reset"
- end="pio_debug_wave.reset" />
<connection
kind="reset"
version="14.1"
@@ -1527,13 +2210,58 @@
<connection
kind="reset"
version="14.1"
- start="cpu_0.debug_reset_request"
- end="avs_eth_0.mm_reset" />
+ start="clk_0.clk_reset"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="ram_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="ram_diag_bg.system_reset" />
<connection
kind="reset"
version="14.1"
start="cpu_0.debug_reset_request"
- end="pio_debug_wave.reset" />
+ end="avs_eth_0.mm_reset" />
<connection
kind="reset"
version="14.1"
@@ -1614,6 +2342,56 @@
version="14.1"
start="cpu_0.debug_reset_request"
end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_bsn_monitor.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="ram_diag_data_buffer.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_diag_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="ram_diag_bg.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2/designs/unb2_test/src/hex/default_eth_header.hex b/boards/uniboard2/designs/unb2_test/src/hex/default_eth_header.hex
new file mode 100644
index 0000000000000000000000000000000000000000..80b6a9bc0f5ed11145fe29952712dae007147b61
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/src/hex/default_eth_header.hex
@@ -0,0 +1,9 @@
+:0800000000074306C7000022BF
+:0800010086080000080045001C
+:080002002322000040007F11E1
+:08000300BA530A6300010A0A66
+:080004000A0A0FA00FA0230E51
+:080005000000000000000000F3
+:080006000000000000000000F2
+:080007000000000000000000F1
+:00000001FF
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index a9144a14fa6d347f6458425830cdf3ef75fa01f7..c2dd310920d4b0a24777a796259e7ab77ea39762 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -24,25 +24,37 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL; --?
+USE common_lib.common_field_pkg.ALL; --?
+USE common_lib.common_network_total_header_pkg.ALL; --?
+USE common_lib.common_network_layers_pkg.ALL; --?
USE unb2_board_lib.unb2_board_pkg.ALL;
USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
+--USE eth_lib.eth_pkg.ALL; --?
+--USE technology_lib.technology_pkg.ALL; --?
+--USE tech_tse_lib.tech_tse_pkg.ALL; --?
+--USE tech_tse_lib.tb_tech_tse_pkg.ALL; --?
USE work.qsys_unb2_test_pkg.ALL;
+
ENTITY mmm_unb2_test IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0
+ g_sim_node_nr : NATURAL := 0;
+ g_nof_streams : NATURAL;
+ g_bg_block_size : NATURAL;
+ g_hdr_field_arr : t_common_field_arr
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
-
+
-- Manual WDI override
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
@@ -69,6 +81,7 @@ ENTITY mmm_unb2_test IS
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso;
+
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
reg_dpmm_data_miso : IN t_mem_miso;
@@ -87,7 +100,40 @@ ENTITY mmm_unb2_test IS
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso
+ reg_remu_miso : IN t_mem_miso;
+
+ -- bg
+ ram_diag_bg_mosi : OUT t_mem_mosi;
+ ram_diag_bg_miso : IN t_mem_miso;
+ reg_diag_bg_mosi : OUT t_mem_mosi;
+ reg_diag_bg_miso : IN t_mem_miso;
+
+ -- dp offload
+ reg_dp_offload_tx_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_miso : IN t_mem_miso;
+
+ reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
+
+ reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
+
+ reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
+
+ -- bsn monitor
+ reg_bsn_monitor_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_miso : IN t_mem_miso;
+
+ -- db
+ ram_diag_data_buf_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_miso : IN t_mem_miso;
+ reg_diag_data_buf_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_miso : IN t_mem_miso;
+
+ -- 10GbE
+ reg_tr_10GbE_mosi : OUT t_mem_mosi;
+ reg_tr_10GbE_miso : IN t_mem_miso
);
END mmm_unb2_test;
@@ -96,6 +142,46 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+ -- Block generator
+ CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
+
+ -- dp_offload
+ CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
+
+ CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
+
+ CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
+ CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
+ CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
+
+ CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
+ CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
+ CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
+
+ -- tr_10GbE
+ CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
+ CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_tr_10GbE_adr_w));
+
+ -- BSN monitors
+ CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb2_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+
+ -- Simulation
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+
+ CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+ --CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+ SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
+ SIGNAL sim_eth_psc_access : STD_LOGIC;
+
+ SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_reg_miso : t_mem_miso;
+
+ SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
@@ -135,10 +221,70 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+
+ u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+
+ u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+ u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+ u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ --u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
+ -- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+
+ ----------------------------------------------------------------------------
+ -- 1GbE setup sequence normally performed by unb_os@NIOS
+ ----------------------------------------------------------------------------
+ p_eth_setup : PROCESS
+ BEGIN
+ sim_eth_mm_bus_switch <= '1';
+
+ eth1g_tse_mosi.wr <= '0';
+ eth1g_tse_mosi.rd <= '0';
+ WAIT FOR 400 ns;
+ WAIT UNTIL rising_edge(mm_clk);
+ -- proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+
+ -- Enable RX
+-- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ sim_eth_mm_bus_switch <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ BEGIN
+ IF sim_eth_mm_bus_switch = '1' THEN
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ ELSE
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ END IF;
+ END PROCESS;
+
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -157,8 +303,6 @@ BEGIN
clk_clk => mm_clk,
reset_reset_n => mm_rst,
- pio_debug_wave_external_connection_export => OPEN,
-
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
pio_wdi_external_connection_export => pout_wdi,
@@ -268,7 +412,88 @@ BEGIN
reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_tr_10gbe_reset_export => OPEN,
+ reg_tr_10gbe_clk_export => OPEN,
+ reg_tr_10gbe_address_export => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
+ reg_tr_10gbe_write_export => reg_tr_10GbE_mosi.wr,
+ reg_tr_10gbe_writedata_export => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_read_export => reg_tr_10GbE_mosi.rd,
+ reg_tr_10gbe_readdata_export => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_waitrequest_export => reg_tr_10GbE_miso.waitrequest,
+
+ reg_bsn_monitor_reset_export => OPEN,
+ reg_bsn_monitor_clk_export => OPEN,
+ reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
+ reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
+ reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
+ reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_offload_tx_reset_export => OPEN,
+ reg_dp_offload_tx_clk_export => OPEN,
+ reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi.wr,
+ reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi.rd,
+ reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_offload_tx_hdr_ovr_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr,
+ reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd,
+ reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_data_buffer_reset_export => OPEN,
+ reg_diag_data_buffer_clk_export => OPEN,
+ reg_diag_data_buffer_address_export => reg_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_write_export => reg_diag_data_buf_mosi.wr,
+ reg_diag_data_buffer_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_read_export => reg_diag_data_buf_mosi.rd,
+ reg_diag_data_buffer_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_data_buffer_clk_export => OPEN,
+ ram_diag_data_buffer_reset_export => OPEN,
+ ram_diag_data_buffer_address_export => ram_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_write_export => ram_diag_data_buf_mosi.wr,
+ ram_diag_data_buffer_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_read_export => ram_diag_data_buf_mosi.rd,
+ ram_diag_data_buffer_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_bg_reset_export => OPEN,
+ reg_diag_bg_clk_export => OPEN,
+ reg_diag_bg_address_export => reg_diag_bg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
+ reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
+ reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_bg_reset_export => OPEN,
+ ram_diag_bg_clk_export => OPEN,
+ ram_diag_bg_address_export => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
+ ram_diag_bg_write_export => ram_diag_bg_mosi.wr,
+ ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_read_export => ram_diag_bg_mosi.rd,
+ ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 5d3d9d57e66f45a859af3a733317acc6c7c583ae..a3d01301eaeffdd978f3b67cd7f9ecff54a0e0c2 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -32,7 +32,6 @@ PACKAGE qsys_unb2_test_pkg IS
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_debug_wave_external_connection_export : out std_logic_vector(31 downto 0); -- export
pio_wdi_external_connection_export : out std_logic; -- export
avs_eth_0_reset_export : out std_logic; -- export
avs_eth_0_clk_export : out std_logic; -- export
@@ -129,7 +128,78 @@ PACKAGE qsys_unb2_test_pkg IS
reg_dpmm_data_write_export : out std_logic; -- export
reg_dpmm_data_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_reset_export : out std_logic -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_tr_10gbe_reset_export : out std_logic; -- export
+ reg_tr_10gbe_clk_export : out std_logic; -- export
+ reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_write_export : out std_logic; -- export
+ reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_read_export : out std_logic; -- export
+ reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_waitrequest_export : in std_logic := 'X'; -- export
+ reg_bsn_monitor_reset_export : out std_logic; -- export
+ reg_bsn_monitor_clk_export : out std_logic; -- export
+ reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_write_export : out std_logic; -- export
+ reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_read_export : out std_logic; -- export
+ reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_write_export : out std_logic; -- export
+ reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_read_export : out std_logic; -- export
+ reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_write_export : out std_logic; -- export
+ reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_read_export : out std_logic; -- export
+ reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_write_export : out std_logic; -- export
+ ram_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_read_export : out std_logic; -- export
+ ram_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
END COMPONENT qsys_unb2_test;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 9f9eb71e825d24bc073bb3fa529bfbe24341c5ef..16fe29787afa5f638e2fa53003358c84a32d98f1 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,17 +20,26 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2_board_lib;
+LIBRARY IEEE, common_lib, unb2_board_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
USE unb2_board_lib.unb2_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
ENTITY unb2_test IS
GENERIC (
g_design_name : STRING := "unb2_test";
g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -40,7 +49,7 @@ ENTITY unb2_test IS
);
PORT (
-- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
+ --CLK : IN STD_LOGIC; -- System Clock - not used as PLL generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -58,7 +67,48 @@ ENTITY unb2_test IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE front and ring
+ SB_CLK : IN STD_LOGIC; -- SerDes Clock 10GbE back
+ BCK_REF_CLK : IN STD_LOGIC; --
+
+ -- back transceivers
+-- BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+-- BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+-- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+-- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+-- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+
+ -- ring transceivers
+-- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+-- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+ -- front transceivers
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_RST : INOUT STD_LOGIC;
+
+ QSFP_LED : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2_test;
@@ -68,16 +118,100 @@ ARCHITECTURE str OF unb2_test IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
+ CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
+
+ -- Revision controlled constants
+ CONSTANT c_use_lpbk : BOOLEAN := FALSE; --g_design_name = "unb2_test_lpbk";
+ CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
+ CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
+ CONSTANT c_nof_streams : NATURAL := 1; --c_unb2_board_tr_qsfp_hw_nof_lines; --FIXME
+ CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
+ sel_a_b(c_use_1GbE, c_eth_data_w,
+ sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
+
+
+ -- Block generator
+ CONSTANT c_bg_block_size : NATURAL := 900;
+ CONSTANT c_bg_gapsize : NATURAL := 100;
+ CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+
+ -- dp_offload_tx
+ CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
+ CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
+
+ CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE;
+ CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
+ CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+
+ CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
+ CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
+
+ CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
+ CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
+ CONSTANT c_nof_crc_words : NATURAL := 1;
+ CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
+ CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
+ CONSTANT c_max_nof_words_per_block : NATURAL := c_bg_block_size;
+ CONSTANT c_min_nof_words_per_block : NATURAL := 1;
+ CONSTANT c_def_nof_words_per_block : NATURAL := sel_a_b(c_use_1GbE, c_def_1GbE_block_size,
+ sel_a_b(c_use_10GbE, c_def_10GbE_block_size,
+ c_bg_block_size));
+ CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
+ CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+
+ SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
+
+
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_ethclk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
- SIGNAL st_rst : STD_LOGIC;
- SIGNAL st_clk : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
@@ -129,6 +263,66 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_remu_mosi : t_mem_mosi;
SIGNAL reg_remu_miso : t_mem_miso;
+ -- 10GbE
+ SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
+ SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 downto 0);
+
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
+
+
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_miso : t_mem_miso;
+
+ SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+ -- Interface: 1GbE UDP streaming ports
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+
+
BEGIN
-----------------------------------------------------------------------------
@@ -136,16 +330,19 @@ BEGIN
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
GENERIC MAP (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb2_board_mm_clk_freq_50M,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb2_board_mm_clk_freq_125M,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams,
+ g_dp_clk_use_pll => FALSE
)
PORT MAP (
-- Clock an reset signals
@@ -157,12 +354,13 @@ BEGIN
mm_clk => mm_clk,
mm_rst => mm_rst,
- dp_rst => st_rst,
- dp_clk => st_clk,
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
+
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -214,9 +412,15 @@ BEGIN
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
-- FPGA pins
-- . General
- CLK => CLK,
+ CLK => '0', -- PLL generated 200MHz dp_clk is used.
PPS => PPS,
WDI => WDI,
INTA => INTA,
@@ -226,10 +430,10 @@ BEGIN
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
- sens_sc => SENS_SC,
- sens_sd => SENS_SD,
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
-- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
+ ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
@@ -241,7 +445,10 @@ BEGIN
GENERIC MAP (
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => 3, --c_nof_streams, --FIXME
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr
)
PORT MAP(
mm_rst => mm_rst,
@@ -295,9 +502,351 @@ BEGIN
-- Remote Update
reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
+ reg_remu_miso => reg_remu_miso,
+
+ -- bg
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ -- dp_offload
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
+
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+ reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ -- bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- db
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- 10GbE
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso
);
+
+
+
+
+
+ -----------------------------------------------------------------------------
+ -- TX: Block generator
+ -----------------------------------------------------------------------------
+ u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP (
+ g_nof_output_streams => c_nof_streams,
+ g_buf_dat_w => c_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
+ );
+
+ -----------------------------------------------------------------------------
+ -- TX: dp_offload_tx
+ -----------------------------------------------------------------------------
+ u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx_dev
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_use_complex => FALSE,
+ g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_def_nof_words_per_block => c_def_nof_words_per_block,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
+ g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_output_fifo_depth => c_max_frame_nof_words,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_ovr_init => c_hdr_field_ovr_init
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_mosi => reg_dp_offload_tx_mosi,
+ reg_miso => reg_dp_offload_tx_miso,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ reg_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+ reg_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+
+ snk_in_arr => block_gen_src_out_arr,
+ snk_out_arr => block_gen_src_in_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
+
+ gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ -- dst = src
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+
+ -- dst port goes through 4000,4001,4002
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
+ END GENERATE;
+
+
+
+-----------------------------------------------------------------------------
+ -- RX: dp_offload_rx
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx_dev
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => NOT(c_use_lpbk),
+ g_crc_nof_words => c_nof_crc_words
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
+ diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
+ END GENERATE;
+
+
+
+
+ -----------------------------------------------------------------------------
+ -- RX: Data buffers and BSN monitors
+ -----------------------------------------------------------------------------
+ dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr;
+
+ gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams-1 GENERATE
+ diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ END GENERATE;
+
+ u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
+ g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+ diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
+
+ u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_nof_streams,
+ g_data_w => 32, --c_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => FALSE -- sync by reading last address of data buffer
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ --in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+
+
+
+ -----------------------------------------------------------------------------
+ -- Interface : Loopback
+ -----------------------------------------------------------------------------
+ gen_loopback : IF c_use_lpbk=TRUE GENERATE
+ dp_offload_rx_snk_in_arr <= dp_offload_tx_src_out_arr;
+ dp_offload_tx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Interface : 1GbE
+ -----------------------------------------------------------------------------
+ gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
+ eth1g_udp_tx_sosi_arr <= dp_offload_tx_src_out_arr;
+ dp_offload_tx_src_in_arr <= eth1g_udp_tx_siso_arr;
+
+ dp_offload_rx_snk_in_arr <= eth1g_udp_rx_sosi_arr;
+ eth1g_udp_rx_siso_arr <= dp_offload_rx_snk_out_arr;
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- tr_10GbE
+ -----------------------------------------------------------------------------
+ gen_tr_10GbE : IF c_use_10GbE=TRUE GENERATE
+ u_tr_10GbE_front_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe_front_and_ring
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_streams,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size*2
+ )
+ PORT MAP (
+ tr_ref_clk => SA_CLK,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ snk_out_arr => dp_offload_tx_src_in_arr,
+ snk_in_arr => dp_offload_tx_src_out_arr,
+
+ -- Serial IO
+ serial_tx_arr => serial_10G_tx_arr,
+ serial_rx_arr => serial_10G_rx_arr
+ );
+
+
+ u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ PORT MAP (
+ serial_tx_arr(0 DOWNTO 0) => serial_10G_tx_arr,
+ serial_rx_arr(0 DOWNTO 0) => serial_10G_rx_arr,
+
+ serial_tx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => (OTHERS=>'0'),
+ serial_rx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 1) => OPEN,
+
+ -- Serial I/O
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ -- QSFP_1_RX => QSFP_1_RX,
+ -- QSFP_1_TX => QSFP_1_TX,
+ -- QSFP_2_RX => QSFP_2_RX,
+ -- QSFP_2_TX => QSFP_2_TX,
+ -- QSFP_3_RX => QSFP_3_RX,
+ -- QSFP_3_TX => QSFP_3_TX,
+ -- QSFP_4_RX => QSFP_4_RX,
+ -- QSFP_4_TX => QSFP_4_TX,
+ -- QSFP_5_RX => QSFP_5_RX,
+ -- QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ --u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
+ --PORT MAP (
+ -- serial_tx_arr => (OTHERS=>'0'),
+ -- --serial_rx_arr => ,
+
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ --);
+
+ --u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
+ --PORT MAP (
+ -- serial_tx_arr => (OTHERS=>'0'),
+ -- --serial_rx_arr => ,
+
+ -- -- Serial I/O
+ -- -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX
+ --);
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index efaf84968c3583433d9562ae2de4906442bfbb26..71708dd95bebc1312be4a94db6363442694f39cf 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -24,6 +24,10 @@ synth_files =
src/vhdl/mms_unb2_board_sens.vhd
src/vhdl/unb2_board_wdi_reg.vhd
src/vhdl/ctrl_unb2_board.vhd
+ src/vhdl/unb2_board_front_io.vhd
+ src/vhdl/unb2_board_back_io.vhd
+ src/vhdl/unb2_board_ring_io.vhd
+ src/vhdl/unb2_board_10gbe.vhd
src/vhdl/unb2_board_peripherals_pkg.vhd
test_bench_files =
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
index 476402179120573cd8c306fcdcfdce0b36dc8530..f36d411a4d55568626dad35839c8d17f723ca4d5 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
@@ -26,8 +26,14 @@ create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK
#create_clock -name {ETH_CLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {ETH_CLK}]
create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports {ETH_CLK}]
-create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
-create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+#create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
+#create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+
+# from Jonathan:
+create_clock -period 1.552 -name {SA_CLK} { SA_CLK }
+create_clock -period 1.552 -name {SB_CLK} { SB_CLK }
+
+
derive_pll_clocks
@@ -48,3 +54,7 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk200]
set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+# from Jonathan:
+set_false_path -from [get_clocks {*cpulse_out_bus[0]}] -to [get_clocks {*wys|clk_divtx_user}]
+set_false_path -from [get_clocks {*wys|clk_divtx_user}] -to [get_clocks {*cpulse_out_bus[0]}]
+
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index c38ea595e3e6775f694d6eff6d135540cbc93661..572f09294310a1ca16b4035f4d34f6035e72919c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -24,7 +24,7 @@
-- . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
-LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib;
+LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -104,9 +104,7 @@ ENTITY ctrl_unb2_board IS
----------------------------------------------------------------------------
g_fpga_temp_high : NATURAL := 85;
g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
- g_dbg_led_red : BOOLEAN := FALSE; -- [when g_app_led_red=FALSE]: when TRUE connect pout_debug_wave to the LEDs; otherwise let ctrl_unb2_board toggle them
g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
- g_dbg_led_green : BOOLEAN := FALSE; -- [when g_app_led_green=FALSE]: when TRUE connect pout_debug_wave to the LEDs; otherwise let ctrl_unb2_board toggle them
g_aux : t_c_unb2_board_aux := c_unb2_board_aux
);
@@ -116,7 +114,7 @@ ENTITY ctrl_unb2_board IS
--
-- System
cs_sim : OUT STD_LOGIC;
- xo_ethclk : OUT STD_LOGIC; -- 25 MHz ETH_clk
+ xo_ethclk : OUT STD_LOGIC; -- 25 MHz ETH_CLK
xo_rst : OUT STD_LOGIC;
xo_rst_n : OUT STD_LOGIC;
@@ -136,10 +134,7 @@ ENTITY ctrl_unb2_board IS
app_led_green : IN STD_LOGIC := '1';
-- PIOs
- pout_debug_wave : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=> '0');
pout_wdi : IN STD_LOGIC; -- Toggled by unb_osy; can be overriden by reg_wdi.
- pin_system_info : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- pin_pps : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- for new designs best use reg_ppsh_mosi/miso
-- Manual WDI override
reg_wdi_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -211,13 +206,13 @@ ENTITY ctrl_unb2_board IS
TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
- sens_sc : INOUT STD_LOGIC := '1';
- sens_sd : INOUT STD_LOGIC := '1';
+ SENS_SC : INOUT STD_LOGIC := '1';
+ SENS_SD : INOUT STD_LOGIC := '1';
-- 1GbE Control Interface
- ETH_clk : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
);
END ctrl_unb2_board;
@@ -288,7 +283,7 @@ BEGIN
TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
-- Clock and reset
- i_xo_ethclk <= ETH_clk; -- use the ETH_clk pin as xo_clk
+ i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
@@ -389,8 +384,6 @@ BEGIN
hw_version => VERSION,
id => ID,
- info => pin_system_info,
-
reg_mosi => reg_unb_system_info_mosi,
reg_miso => reg_unb_system_info_miso,
@@ -412,13 +405,7 @@ BEGIN
END GENERATE;
no_app_led_red: IF g_app_led_red = FALSE GENERATE
- gen_dbg_led_red: IF g_dbg_led_red = TRUE GENERATE
- TESTIO(c_unb2_board_testio_led_red) <= pout_debug_wave(pout_debug_wave'HIGH); -- [31]
- END GENERATE;
-
- gen_toggle_led_red: IF g_dbg_led_red = FALSE GENERATE
- TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
- END GENERATE;
+ TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
END GENERATE;
@@ -432,21 +419,15 @@ BEGIN
END GENERATE;
no_app_led_green: IF g_app_led_green = FALSE GENERATE
- gen_dbg_led_green: IF g_dbg_led_green = TRUE GENERATE
- TESTIO(c_unb2_board_testio_led_green) <= pout_debug_wave(pout_debug_wave'HIGH-1); -- [30]
- END GENERATE;
-
- gen_toggle_led_green: IF g_dbg_led_green = FALSE GENERATE
- TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
- END GENERATE;
+ TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
END GENERATE;
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
- led_toggle_red <= sel_a_b(g_design_name(1 TO 12)="unb2_minimal", led_toggle, '0');
- led_toggle_green <= sel_a_b(g_design_name(1 TO 12)/="unb2_minimal", led_toggle, '0');
+ led_toggle_red <= sel_a_b(g_design_name(1 TO 8)="unb2_min", led_toggle, '0');
+ led_toggle_green <= sel_a_b(g_design_name(1 TO 8)/="unb2_min", led_toggle, '0');
u_toggle : ENTITY common_lib.common_toggle
PORT MAP (
@@ -546,9 +527,6 @@ BEGIN
reg_mosi => reg_ppsh_mosi,
reg_miso => reg_ppsh_miso,
- -- Old PIO support (for backwards compatibility with pin_pps on ctrl_unb2_board)
- pin_pps => pin_pps,
-
-- Streaming clock domain
pps_sys => dp_pps
);
@@ -577,8 +555,8 @@ BEGIN
reg_miso => reg_unb_sens_miso,
-- i2c bus
- scl => sens_sc,
- sda => sens_sd,
+ scl => SENS_SC,
+ sda => SENS_SD,
-- Temperature alarm
temp_alarm => temp_alarm
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e44c32d2bd85c7172790ab724260ff3b23777f5a
--- /dev/null
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_10gbe_front_and_ring IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10;
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_macs : NATURAL;
+ g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
+ g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
+ g_word_alignment_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ tr_ref_clk : IN STD_LOGIC := '0';
+
+ -- MM interface
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ reg_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mac_miso : OUT t_mem_miso;
+
+ -- DP interface
+ dp_rst : IN STD_LOGIC := '0';
+ dp_clk : IN STD_LOGIC := '0';
+
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+
+ src_in_arr : IN t_dp_siso_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+
+ -- Serial IO
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0')
+ );
+END unb2_board_10gbe_front_and_ring;
+
+
+ARCHITECTURE str OF unb2_board_10gbe_front_and_ring IS
+
+ SIGNAL tr_ref_clk_312 : STD_LOGIC;
+ SIGNAL tr_ref_clk_156 : STD_LOGIC;
+ SIGNAL tr_ref_rst_156 : STD_LOGIC;
+
+BEGIN
+ u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+
+ u_tr_10GbE_front_and_ring: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => g_nof_macs,
+ g_tx_fifo_fill => g_tx_fifo_fill,
+ g_tx_fifo_size => g_tx_fifo_size
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_mac_mosi,
+ reg_mac_miso => reg_mac_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+
+END str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..37d5c14ced31b82bce63111c5ca8972d585ee9ac
--- /dev/null
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -0,0 +1,61 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_back_io IS
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+
+ -- back transceivers
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+ BCK_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.bus_w-1 downto 0);
+
+ BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+ BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
+ BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0)
+ );
+END unb2_board_back_io;
+
+ARCHITECTURE str OF unb2_board_back_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_back_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+ connect_back : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
+ BCK_TX(i) <= si_tx_arr(i);
+ si_rx_arr(i) <= BCK_RX(i);
+ END GENERATE;
+
+
+ wire_signals : FOR i IN 0 TO c_unb2_board_tr_back_hw_nof_lines-1 GENERATE
+ si_tx_arr(i) <= serial_tx_arr(i);
+ serial_rx_arr(i) <= si_rx_arr(i);
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4ce79654aecc4f6d8d9cd7294d775b228b3ae0cd
--- /dev/null
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -0,0 +1,128 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_front_io IS
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(0 downto 0); --c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+-- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_RST : INOUT STD_LOGIC;
+
+ QSFP_LED : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2_board_front_io;
+
+ARCHITECTURE str OF unb2_board_front_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+ QSFP_0_TX(0) <= si_tx_arr(0);
+ -- QSFP_0_TX(1) <= si_tx_arr(1);
+ -- QSFP_0_TX(2) <= si_tx_arr(2);
+ -- QSFP_0_TX(3) <= si_tx_arr(3);
+
+ -- QSFP_1_TX(0) <= si_tx_arr(4);
+ -- QSFP_1_TX(1) <= si_tx_arr(5);
+ -- QSFP_1_TX(2) <= si_tx_arr(6);
+ -- QSFP_1_TX(3) <= si_tx_arr(7);
+
+ -- QSFP_2_TX(0) <= si_tx_arr(8);
+ -- QSFP_2_TX(1) <= si_tx_arr(9);
+ -- QSFP_2_TX(2) <= si_tx_arr(10);
+ -- QSFP_2_TX(3) <= si_tx_arr(11);
+
+ -- QSFP_3_TX(0) <= si_tx_arr(12);
+ -- QSFP_3_TX(1) <= si_tx_arr(13);
+ -- QSFP_3_TX(2) <= si_tx_arr(14);
+ -- QSFP_3_TX(3) <= si_tx_arr(15);
+
+ -- QSFP_4_TX(0) <= si_tx_arr(16);
+ -- QSFP_4_TX(1) <= si_tx_arr(17);
+ -- QSFP_4_TX(2) <= si_tx_arr(18);
+ -- QSFP_4_TX(3) <= si_tx_arr(19);
+
+ -- QSFP_5_TX(0) <= si_tx_arr(20);
+ -- QSFP_5_TX(1) <= si_tx_arr(21);
+ -- QSFP_5_TX(2) <= si_tx_arr(22);
+ -- QSFP_5_TX(3) <= si_tx_arr(23);
+
+
+ si_rx_arr(0) <= QSFP_0_RX(0);
+ --si_rx_arr(1) <= QSFP_0_RX(1);
+ --si_rx_arr(2) <= QSFP_0_RX(2);
+ --si_rx_arr(3) <= QSFP_0_RX(3);
+
+ --si_rx_arr(4) <= QSFP_1_RX(0);
+ --si_rx_arr(5) <= QSFP_1_RX(1);
+ --si_rx_arr(6) <= QSFP_1_RX(2);
+ --si_rx_arr(7) <= QSFP_1_RX(3);
+
+ --si_rx_arr(8) <= QSFP_2_RX(0);
+ --si_rx_arr(9) <= QSFP_2_RX(1);
+ --si_rx_arr(10) <= QSFP_2_RX(2);
+ --si_rx_arr(11) <= QSFP_2_RX(3);
+
+ --si_rx_arr(12) <= QSFP_3_RX(0);
+ --si_rx_arr(13) <= QSFP_3_RX(1);
+ --si_rx_arr(14) <= QSFP_3_RX(2);
+ --si_rx_arr(15) <= QSFP_3_RX(3);
+
+ --si_rx_arr(16) <= QSFP_4_RX(0);
+ --si_rx_arr(17) <= QSFP_4_RX(1);
+ --si_rx_arr(18) <= QSFP_4_RX(2);
+ --si_rx_arr(19) <= QSFP_4_RX(3);
+
+ --si_rx_arr(20) <= QSFP_5_RX(0);
+ --si_rx_arr(21) <= QSFP_5_RX(1);
+ --si_rx_arr(22) <= QSFP_5_RX(2);
+ --si_rx_arr(23) <= QSFP_5_RX(3);
+
+
+ wire_signals : FOR i IN 0 TO c_unb2_board_tr_qsfp_hw_nof_lines-1 GENERATE
+ si_tx_arr(i) <= serial_tx_arr(i);
+ serial_rx_arr(i) <= si_rx_arr(i);
+ END GENERATE;
+
+END;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index adc18e48bb357962c9a12fa684b164c7f6c7842a..bb3098261ea2c6bb992d8b8a8290cdb626e92995 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -64,7 +64,30 @@ PACKAGE unb2_board_pkg IS
CONSTANT c_unb2_board_signature_eth1g : INTEGER := TO_SINT(c_unb2_board_signature_eth1g_slv );
CONSTANT c_unb2_board_signature_eth10g : INTEGER := TO_SINT(c_unb2_board_signature_eth10g_slv );
-
+ -- Transceivers
+ TYPE t_c_unb2_board_tr IS RECORD
+ nof_bus : NATURAL;
+ bus_w : NATURAL;
+ i2c_w : NATURAL;
+ END RECORD;
+
+ CONSTANT c_unb2_board_tr_back : t_c_unb2_board_tr := (1, 48, 3); -- per node: 1 bus with 48 channels
+ CONSTANT c_unb2_board_tr_ring : t_c_unb2_board_tr := (2, 12, 0); -- per node: 2 buses with 12 channels
+ CONSTANT c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
+ CONSTANT c_unb2_board_tr_qsfp_nof_leds : NATURAL := 12;
+
+ -- Transceivers network array types for the UniBoard mesh HW and for a backplane HW
+ CONSTANT c_unb2_board_tr_back_hw_nof_bus : NATURAL := 1;
+ CONSTANT c_unb2_board_tr_back_hw_bus_w : NATURAL := 48;
+ CONSTANT c_unb2_board_tr_ring_hw_nof_bus : NATURAL := 2;
+ CONSTANT c_unb2_board_tr_ring_hw_bus_w : NATURAL := 12;
+ CONSTANT c_unb2_board_tr_qsfp_hw_nof_bus : NATURAL := 6;
+ CONSTANT c_unb2_board_tr_qsfp_hw_bus_w : NATURAL := 4;
+
+ CONSTANT c_unb2_board_tr_qsfp_hw_nof_lines : NATURAL := (c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w);
+ CONSTANT c_unb2_board_tr_back_hw_nof_lines : NATURAL := (c_unb2_board_tr_back.nof_bus * c_unb2_board_tr_back.bus_w);
+ CONSTANT c_unb2_board_tr_ring_hw_nof_lines : NATURAL := (c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w);
+
-- Auxiliary
-- Test IO Interface
@@ -93,15 +116,6 @@ PACKAGE unb2_board_pkg IS
TYPE t_e_unb2_board_node IS (e_any);
- -- UniBoard Common Interface
- TYPE t_c_unb2_board_ci IS RECORD
- aux : t_c_unb2_board_aux;
- END RECORD;
-
- -- FIXME: this does not compile in modelsim: (pls compare with unb1_board_pkg.vhd)
- --CONSTANT c_unb2_board_ci : t_c_unb2_board_ci := (c_unb2_board_aux);
-
-
TYPE t_unb2_board_fw_version IS RECORD
hi : NATURAL; -- = 0..15
lo : NATURAL; -- = 0..15, firmware version is: hi.lo
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f68e84df81e458456d5acd97e1219183278dae09
--- /dev/null
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -0,0 +1,107 @@
+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.unb2_board_pkg.ALL;
+
+
+ENTITY unb2_board_ring_io IS
+ PORT (
+ serial_tx_arr : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+ serial_rx_arr : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0)
+ );
+END unb2_board_ring_io;
+
+ARCHITECTURE str OF unb2_board_ring_io IS
+
+ -- help signals so we can iterate through buses
+ SIGNAL si_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL si_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_ring_hw_nof_lines-1 DOWNTO 0);
+
+BEGIN
+
+ RING_0_TX(0) <= si_tx_arr(0);
+ RING_0_TX(1) <= si_tx_arr(1);
+ RING_0_TX(2) <= si_tx_arr(2);
+ RING_0_TX(3) <= si_tx_arr(3);
+ RING_0_TX(4) <= si_tx_arr(4);
+ RING_0_TX(5) <= si_tx_arr(5);
+ RING_0_TX(6) <= si_tx_arr(6);
+ RING_0_TX(7) <= si_tx_arr(7);
+ RING_0_TX(8) <= si_tx_arr(8);
+ RING_0_TX(9) <= si_tx_arr(9);
+ RING_0_TX(10) <= si_tx_arr(10);
+ RING_0_TX(11) <= si_tx_arr(11);
+
+ RING_1_TX(0) <= si_tx_arr(12);
+ RING_1_TX(1) <= si_tx_arr(13);
+ RING_1_TX(2) <= si_tx_arr(14);
+ RING_1_TX(3) <= si_tx_arr(15);
+ RING_1_TX(4) <= si_tx_arr(16);
+ RING_1_TX(5) <= si_tx_arr(17);
+ RING_1_TX(6) <= si_tx_arr(18);
+ RING_1_TX(7) <= si_tx_arr(19);
+ RING_1_TX(8) <= si_tx_arr(20);
+ RING_1_TX(9) <= si_tx_arr(21);
+ RING_1_TX(10) <= si_tx_arr(22);
+ RING_1_TX(11) <= si_tx_arr(23);
+
+
+ si_rx_arr(0) <= RING_0_RX(0);
+ si_rx_arr(1) <= RING_0_RX(1);
+ si_rx_arr(2) <= RING_0_RX(2);
+ si_rx_arr(3) <= RING_0_RX(3);
+ si_rx_arr(4) <= RING_0_RX(4);
+ si_rx_arr(5) <= RING_0_RX(5);
+ si_rx_arr(6) <= RING_0_RX(6);
+ si_rx_arr(7) <= RING_0_RX(7);
+ si_rx_arr(8) <= RING_0_RX(8);
+ si_rx_arr(9) <= RING_0_RX(9);
+ si_rx_arr(10) <= RING_0_RX(10);
+ si_rx_arr(11) <= RING_0_RX(11);
+
+ si_rx_arr(12) <= RING_1_RX(0);
+ si_rx_arr(13) <= RING_1_RX(1);
+ si_rx_arr(14) <= RING_1_RX(2);
+ si_rx_arr(15) <= RING_1_RX(3);
+ si_rx_arr(16) <= RING_1_RX(4);
+ si_rx_arr(17) <= RING_1_RX(5);
+ si_rx_arr(18) <= RING_1_RX(6);
+ si_rx_arr(19) <= RING_1_RX(7);
+ si_rx_arr(20) <= RING_1_RX(8);
+ si_rx_arr(21) <= RING_1_RX(9);
+ si_rx_arr(22) <= RING_1_RX(10);
+ si_rx_arr(23) <= RING_1_RX(11);
+
+
+ wire_signals : FOR i IN 0 TO c_unb2_board_tr_ring_hw_nof_lines-1 GENERATE
+ si_tx_arr(i) <= serial_tx_arr(i);
+ serial_rx_arr(i) <= si_rx_arr(i);
+ END GENERATE;
+
+END;