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RTSD
HDL
Commits
c50f5fc5
Commit
c50f5fc5
authored
2 years ago
by
Eric Kooistra
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Correct compile errors in eth_stream.vhd.
parent
8085c32c
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!293
Rename eth_stream into eth_stream_udp. Create new eth_stream.vhd that contains...
Pipeline
#39960
passed
2 years ago
Stage: simulation
Stage: synthesis
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libraries/io/eth/hdllib.cfg
+1
-0
1 addition, 0 deletions
libraries/io/eth/hdllib.cfg
libraries/io/eth/src/vhdl/eth_stream.vhd
+10
-10
10 additions, 10 deletions
libraries/io/eth/src/vhdl/eth_stream.vhd
with
11 additions
and
10 deletions
libraries/io/eth/hdllib.cfg
+
1
−
0
View file @
c50f5fc5
...
...
@@ -23,6 +23,7 @@ synth_files =
src/vhdl/eth_ihl_to_20.vhd
src/vhdl/eth.vhd
src/vhdl/eth_stream_udp.vhd
src/vhdl/eth_stream.vhd
src/vhdl/eth_tester_pkg.vhd
src/vhdl/eth_tester_tx.vhd
src/vhdl/eth_tester_rx.vhd
...
...
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libraries/io/eth/src/vhdl/eth_stream.vhd
+
10
−
10
View file @
c50f5fc5
...
...
@@ -39,18 +39,20 @@
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
LIBRARY
IEEE
,
common_lib
,
dp_lib
,
tech_tse_lib
;
LIBRARY
IEEE
,
common_lib
,
dp_lib
,
technology_lib
,
tech_tse_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
dp_lib
.
dp_stream_pkg
.
ALL
;
USE
tech_tse_lib
.
tech_tse_pkg
.
ALL
;
USE
work
.
eth_pkg
.
ALL
;
USE
technology_lib
.
technology_select_pkg
.
ALL
;
ENTITY
eth_stream
IS
GENERIC
(
g_technology
:
NATURAL
:
=
c_tech_select_default
;
g_ETH_PHY
:
STRING
:
=
"LVDS"
;
-- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_rx_udp_port
:
NATURAL
:
=
c_eth_rx_udp_port
;
g_rx_udp_port
:
NATURAL
:
=
TO_UINT
(
c_eth_rx_udp_port
)
;
g_jumbo_en
:
BOOLEAN
:
=
FALSE
;
g_sim
:
BOOLEAN
:
=
FALSE
;
g_sim_level
:
NATURAL
:
=
0
-- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
...
...
@@ -136,17 +138,15 @@ BEGIN
g_ETH_PHY
=>
g_ETH_PHY
,
g_jumbo_en
=>
g_jumbo_en
,
g_sim
=>
g_sim
,
g_sim_level
=>
g_sim_level
,
g_sim_tx
=>
g_sim_tx
,
g_sim_rx
=>
g_sim_rx
g_sim_level
=>
g_sim_level
)
PORT
MAP
(
-- Clocks and reset
mm_rst
=>
mm_rst
;
mm_clk
=>
mm_clk
;
-- MM
eth_clk
=>
eth_clk
;
-- 125 MHz
tx_snk_clk
=>
st_rst
;
-- DP
rx_src_clk
=>
st_clk
;
-- DP
mm_rst
=>
mm_rst
,
mm_clk
=>
mm_clk
,
-- MM
eth_clk
=>
eth_clk
,
-- 125 MHz
tx_snk_clk
=>
st_rst
,
-- DP
rx_src_clk
=>
st_clk
,
-- DP
-- TSE setup
src_mac
=>
src_mac
,
...
...
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