From c50f5fc5c61dea5a3d593d49a190220ff6101d64 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 23 Nov 2022 10:35:31 +0100
Subject: [PATCH] Correct compile errors in eth_stream.vhd.
---
libraries/io/eth/hdllib.cfg | 1 +
libraries/io/eth/src/vhdl/eth_stream.vhd | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 742f78eb91..39fcfc924d 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -23,6 +23,7 @@ synth_files =
src/vhdl/eth_ihl_to_20.vhd
src/vhdl/eth.vhd
src/vhdl/eth_stream_udp.vhd
+ src/vhdl/eth_stream.vhd
src/vhdl/eth_tester_pkg.vhd
src/vhdl/eth_tester_tx.vhd
src/vhdl/eth_tester_rx.vhd
diff --git a/libraries/io/eth/src/vhdl/eth_stream.vhd b/libraries/io/eth/src/vhdl/eth_stream.vhd
index a1e5c40ed6..f52db7aaff 100644
--- a/libraries/io/eth/src/vhdl/eth_stream.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream.vhd
@@ -39,18 +39,20 @@
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
-LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE work.eth_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY eth_stream IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
- g_rx_udp_port : NATURAL := c_eth_rx_udp_port;
+ g_rx_udp_port : NATURAL := TO_UINT(c_eth_rx_udp_port);
g_jumbo_en : BOOLEAN := FALSE;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
@@ -136,17 +138,15 @@ BEGIN
g_ETH_PHY => g_ETH_PHY,
g_jumbo_en => g_jumbo_en,
g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_sim_tx => g_sim_tx,
- g_sim_rx => g_sim_rx
+ g_sim_level => g_sim_level
)
PORT MAP (
-- Clocks and reset
- mm_rst => mm_rst;
- mm_clk => mm_clk; -- MM
- eth_clk => eth_clk; -- 125 MHz
- tx_snk_clk => st_rst; -- DP
- rx_src_clk => st_clk; -- DP
+ mm_rst => mm_rst,
+ mm_clk => mm_clk, -- MM
+ eth_clk => eth_clk, -- 125 MHz
+ tx_snk_clk => st_rst, -- DP
+ rx_src_clk => st_clk, -- DP
-- TSE setup
src_mac => src_mac,
--
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