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Commit 8085c32c authored by Eric Kooistra's avatar Eric Kooistra
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Rename eth_stream into eth_stream_udp. Create new eth_stream.vhd that contains...

Rename eth_stream into eth_stream_udp. Create new eth_stream.vhd that contains complete ETH interface component with eth_stream_udp and tech_tse_with_setup.
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1 merge request!293Rename eth_stream into eth_stream_udp. Create new eth_stream.vhd that contains...
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......@@ -22,7 +22,7 @@ synth_files =
src/vhdl/eth_control.vhd
src/vhdl/eth_ihl_to_20.vhd
src/vhdl/eth.vhd
src/vhdl/eth_stream.vhd
src/vhdl/eth_stream_udp.vhd
src/vhdl/eth_tester_pkg.vhd
src/vhdl/eth_tester_tx.vhd
src/vhdl/eth_tester_rx.vhd
......@@ -36,10 +36,10 @@ test_bench_files =
tb/vhdl/tb_eth.vhd
tb/vhdl/tb_eth_tester_pkg.vhd
tb/vhdl/tb_eth_tester.vhd
tb/vhdl/tb_eth_stream.vhd
tb/vhdl/tb_eth_stream_udp.vhd
tb/vhdl/tb_tb_eth.vhd
tb/vhdl/tb_tb_eth_tester.vhd
tb/vhdl/tb_tb_eth_stream.vhd
tb/vhdl/tb_tb_eth_stream_udp.vhd
tb/vhdl/tb_eth_udp_offload.vhd
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_tb_eth_regression.vhd
......@@ -52,7 +52,7 @@ regression_test_vhdl =
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_eth.vhd
tb/vhdl/tb_tb_eth_tester.vhd
tb/vhdl/tb_tb_eth_stream.vhd
tb/vhdl/tb_tb_eth_stream_udp.vhd
[modelsim_project_file]
......
......@@ -22,164 +22,158 @@
-- Author: Eric Kooistra
-- Purpose:
-- Provide Ethernet access to a node for one UDP stream.
-- Provide Ethernet access to a node for one UDP stream via TSE.
-- Description:
-- * This eth_stream.vhd is a stripped down version of eth.vhd.
-- * This eth_stream only contains the components that are needed to send or
-- receive an UDP stream via 1GbE.
-- The IP checksum is filled in for Tx and checked or Rx.
-- The Tx only contains UDP stream data, so no need for a dp_mux.
-- The Rx may contain other packet types, because the 1GbE connects to a
-- network. All Rx packets that are not UDP for g_rx_udp_port are discarded.
-- * This eth_stream.vhd is a stripped down version of eth.vhd to offload and
-- onload one UDP stream.
-- . see eth_stream_udp.vhd for UDP offload/onload stream details
-- . contains the TSE
-- . sets up TSE in state machnine and then switch to external mm_ctlr,
-- when setup_done = '1', to allow external monitoring of the TSE
-- . use g_jumbo_en = FALSE to support 1500 octet frames 1518 like in
-- unb_osy/unbos_eth.h, or use g_jumbo_en = TRUE to support 9000 octet
-- frames. With g_jumbo_en = FALSE a 9000 octet packet is received
-- properly, but has rx_src_out.err = 3 indicating invalid length.
-- Use c_jumbo_en = TRUE to avoid invalid length.
--
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
LIBRARY IEEE, common_lib, dp_lib;
LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE work.eth_pkg.ALL;
ENTITY eth_stream IS
GENERIC (
g_rx_udp_port : NATURAL
g_technology : NATURAL := c_tech_select_default;
g_ETH_PHY : STRING := "LVDS"; -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_rx_udp_port : NATURAL := c_eth_rx_udp_port;
g_jumbo_en : BOOLEAN := FALSE;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
);
PORT (
-- Clocks and reset
st_rst : IN STD_LOGIC;
st_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
eth_clk : IN STD_LOGIC; -- ethernet phy reference clock
st_rst : IN STD_LOGIC; -- reset synchronous with st_clk
st_clk : IN STD_LOGIC; -- packet stream clock
-- User UDP interface
-- . Tx
udp_tx_sosi : IN t_dp_sosi;
udp_tx_siso : OUT t_dp_siso;
-- . Rx
udp_rx_sosi : OUT t_dp_sosi;
udp_rx_siso : IN t_dp_siso := c_dp_siso_rdy;
cal_rec_clk : IN STD_LOGIC := '0'; -- Calibration & reconfig clock when using XCVR
-- TSE setup
src_mac : IN STD_LOGIC_VECTOR(c_48-1 DOWNTO 0);
setup_done : OUT STD_LOGIC;
-- UDP transmit interface
udp_tx_snk_in : IN t_dp_sosi := c_dp_sosi_rst;
udp_tx_snk_out : OUT t_dp_siso;
-- UDP receive interface
udp_rx_src_in : IN t_dp_siso := c_dp_siso_rdy;
udp_rx_src_out : OUT t_dp_sosi;
-- Memory Mapped Slaves
tse_ctlr_copi : IN t_mem_mosi; -- ETH TSE MAC registers
tse_ctlr_cipo : OUT t_mem_miso;
-- PHY interface
-- . Tx
tse_tx_sosi : OUT t_dp_sosi;
tse_tx_siso : IN t_dp_siso;
-- . Rx
tse_rx_sosi : IN t_dp_sosi;
tse_rx_siso : OUT t_dp_siso
eth_txp : OUT STD_LOGIC;
eth_rxp : IN STD_LOGIC;
-- LED interface
tse_led : OUT t_tech_tse_led
);
END eth_stream;
ARCHITECTURE str OF eth_stream IS
-- ETH Tx
SIGNAL eth_tx_siso : t_dp_siso;
SIGNAL eth_tx_sosi : t_dp_sosi;
-- ETH Rx
SIGNAL rx_adapt_siso : t_dp_siso;
SIGNAL rx_adapt_sosi : t_dp_sosi;
-- Tx UDP offload stream to TSE
SIGNAL tse_tx_sosi : t_dp_sosi;
SIGNAL tse_tx_siso : t_dp_siso;
SIGNAL rx_hdr_status : t_eth_hdr_status;
SIGNAL rx_hdr_status_complete : STD_LOGIC;
SIGNAL rx_eth_discard : STD_LOGIC;
SIGNAL rx_eth_discard_val : STD_LOGIC;
-- Rx stream from TSE (contains the UDP onload packets and possibly other
-- network packets)
SIGNAL tse_rx_sosi : t_dp_sosi;
SIGNAL tse_rx_siso : t_dp_siso;
BEGIN
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
-- Insert IP header checksum
u_tx_ip : ENTITY work.eth_hdr
u_eth_stream_udp : ENTITY work.eth_stream_udp
GENERIC MAP (
g_header_store_and_forward => TRUE,
g_ip_header_checksum_calculate => TRUE
g_rx_udp_port => g_rx_udp_port
)
PORT MAP (
-- Clocks and reset
rst => st_rst,
clk => st_clk,
-- Streaming Sink
snk_in => udp_tx_sosi,
snk_out => udp_tx_siso,
-- Streaming Source
src_in => tse_tx_siso,
src_out => tse_tx_sosi -- with err field value 0 for OK
);
st_rst => st_rst,
st_clk => st_clk,
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
-- User UDP interface
-- . Tx
udp_tx_sosi => udp_tx_snk_in,
udp_tx_siso => udp_tx_snk_out,
-- . Rx
udp_rx_sosi => udp_rx_src_out,
udp_rx_siso => udp_rx_src_in,
-- Adapt the TSE RX source ready latency from 2 to 1
u_adapt : ENTITY dp_lib.dp_latency_adapter
GENERIC MAP (
g_in_latency => c_eth_rx_ready_latency, -- = 2
g_out_latency => c_eth_ready_latency -- = 1
)
PORT MAP (
rst => st_rst,
clk => st_clk,
-- ST sink
snk_out => tse_rx_siso,
snk_in => tse_rx_sosi,
-- ST source
src_in => rx_adapt_siso,
src_out => rx_adapt_sosi
-- PHY interface
-- . Tx
tse_tx_sosi => tse_tx_sosi,
tse_tx_siso => tse_tx_siso,
-- . Rx
tse_rx_sosi => tse_rx_sosi,
tse_rx_siso => tse_tx_siso
);
-- Pass on UDP stream for g_rx_udp_port
-- . Verify IP header checksum for IP
u_rx_udp : ENTITY work.eth_hdr
u_tech_tse_with_setup : ENTITY tech_tse_lib.tech_tse_with_setup
GENERIC MAP (
g_header_store_and_forward => TRUE,
g_ip_header_checksum_calculate => TRUE
g_technology => g_technology,
g_ETH_PHY => g_ETH_PHY,
g_jumbo_en => g_jumbo_en,
g_sim => g_sim,
g_sim_level => g_sim_level,
g_sim_tx => g_sim_tx,
g_sim_rx => g_sim_rx
)
PORT MAP (
-- Clocks and reset
rst => st_rst,
clk => st_clk,
mm_rst => mm_rst;
mm_clk => mm_clk; -- MM
eth_clk => eth_clk; -- 125 MHz
tx_snk_clk => st_rst; -- DP
rx_src_clk => st_clk; -- DP
-- Streaming Sink
snk_in => rx_adapt_sosi,
snk_out => rx_adapt_siso,
-- TSE setup
src_mac => src_mac,
setup_done => setup_done,
-- Streaming Source
src_in => udp_rx_siso,
src_out => udp_rx_sosi,
-- Calibration & reconfig clock
cal_rec_clk => cal_rec_clk,
-- Frame control
frm_discard => rx_eth_discard,
frm_discard_val => rx_eth_discard_val,
-- Memory Mapped Peripheral
mm_ctlr_copi => tse_ctlr_copi,
mm_ctlr_cipo => tse_ctlr_cipo,
-- Header info
hdr_status => rx_hdr_status,
hdr_status_complete => rx_hdr_status_complete
);
-- MAC transmit interface
-- . ST sink
tx_snk_in => tse_tx_sosi,
tx_snk_out => tse_tx_siso,
-- Discard all Rx data that is not UDP for g_rx_udp_port
p_rx_discard : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst = '1' THEN
rx_eth_discard <= '1'; -- default discard
rx_eth_discard_val <= '0';
ELSIF rising_edge(st_clk) THEN
-- Default keep rx_eth_discard status (instead of '1'), to more clearly
-- see when a change occurs
IF rx_hdr_status_complete = '1' THEN
rx_eth_discard <= '1'; -- default discard
IF rx_hdr_status.is_ip = '1' AND
rx_hdr_status.is_udp = '1' AND
TO_UINT(rx_hdr_status.udp_port) = g_rx_udp_port THEN
rx_eth_discard <= '0'; -- pass on IP/UDP stream for g_rx_udp_port
END IF;
END IF;
rx_eth_discard_val <= rx_hdr_status_complete;
END IF;
END PROCESS;
-- MAC receive interface
-- . ST Source
rx_src_in => tse_rx_siso,
rx_src_out => tse_rx_sosi,
-- PHY interface
eth_txp => eth_txp,
eth_rxp => eth_rxp,
tse_led => tse_led
);
END str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2022
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: Eric Kooistra
-- Purpose:
-- Provide Ethernet access to a node for one UDP stream.
-- Description:
-- * This eth_stream_udp.vhd contains the IP/UDP related components of eth.vhd
-- that are needed to send or receive an UDP stream via 1GbE.
-- . support only only UDP offload/onload stream.
-- . the IP checksum is filled in for Tx and checked or Rx.
-- . the Tx only contains UDP stream data, so no need for a dp_mux.
-- . the Rx may contain other packet types, because the 1GbE connects to
-- a network. All Rx packets that are not UDP for g_rx_udp_port are
-- discarded.
-- * Use eth_stream.vhd to have eth_stream_udp in combination with the TSE.
--
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.eth_pkg.ALL;
ENTITY eth_stream_udp IS
GENERIC (
g_rx_udp_port : NATURAL
);
PORT (
-- Clocks and reset
st_rst : IN STD_LOGIC;
st_clk : IN STD_LOGIC;
-- User UDP interface
-- . Tx
udp_tx_sosi : IN t_dp_sosi;
udp_tx_siso : OUT t_dp_siso;
-- . Rx
udp_rx_sosi : OUT t_dp_sosi;
udp_rx_siso : IN t_dp_siso := c_dp_siso_rdy;
-- PHY interface
-- . Tx
tse_tx_sosi : OUT t_dp_sosi;
tse_tx_siso : IN t_dp_siso;
-- . Rx
tse_rx_sosi : IN t_dp_sosi;
tse_rx_siso : OUT t_dp_siso
);
END eth_stream_udp;
ARCHITECTURE str OF eth_stream_udp IS
-- ETH Tx
SIGNAL eth_tx_siso : t_dp_siso;
SIGNAL eth_tx_sosi : t_dp_sosi;
-- ETH Rx
SIGNAL rx_adapt_siso : t_dp_siso;
SIGNAL rx_adapt_sosi : t_dp_sosi;
SIGNAL rx_hdr_status : t_eth_hdr_status;
SIGNAL rx_hdr_status_complete : STD_LOGIC;
SIGNAL rx_eth_discard : STD_LOGIC;
SIGNAL rx_eth_discard_val : STD_LOGIC;
BEGIN
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
-- Insert IP header checksum
u_tx_ip : ENTITY work.eth_hdr
GENERIC MAP (
g_header_store_and_forward => TRUE,
g_ip_header_checksum_calculate => TRUE
)
PORT MAP (
-- Clocks and reset
rst => st_rst,
clk => st_clk,
-- Streaming Sink
snk_in => udp_tx_sosi,
snk_out => udp_tx_siso,
-- Streaming Source
src_in => tse_tx_siso,
src_out => tse_tx_sosi -- with err field value 0 for OK
);
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
-- Adapt the TSE RX source ready latency from 2 to 1
u_adapt : ENTITY dp_lib.dp_latency_adapter
GENERIC MAP (
g_in_latency => c_eth_rx_ready_latency, -- = 2
g_out_latency => c_eth_ready_latency -- = 1
)
PORT MAP (
rst => st_rst,
clk => st_clk,
-- ST sink
snk_out => tse_rx_siso,
snk_in => tse_rx_sosi,
-- ST source
src_in => rx_adapt_siso,
src_out => rx_adapt_sosi
);
-- Pass on UDP stream for g_rx_udp_port
-- . Verify IP header checksum for IP
u_rx_udp : ENTITY work.eth_hdr
GENERIC MAP (
g_header_store_and_forward => TRUE,
g_ip_header_checksum_calculate => TRUE
)
PORT MAP (
-- Clocks and reset
rst => st_rst,
clk => st_clk,
-- Streaming Sink
snk_in => rx_adapt_sosi,
snk_out => rx_adapt_siso,
-- Streaming Source
src_in => udp_rx_siso,
src_out => udp_rx_sosi,
-- Frame control
frm_discard => rx_eth_discard,
frm_discard_val => rx_eth_discard_val,
-- Header info
hdr_status => rx_hdr_status,
hdr_status_complete => rx_hdr_status_complete
);
-- Discard all Rx data that is not UDP for g_rx_udp_port
p_rx_discard : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst = '1' THEN
rx_eth_discard <= '1'; -- default discard
rx_eth_discard_val <= '0';
ELSIF rising_edge(st_clk) THEN
-- Default keep rx_eth_discard status (instead of '1'), to more clearly
-- see when a change occurs
IF rx_hdr_status_complete = '1' THEN
rx_eth_discard <= '1'; -- default discard
IF rx_hdr_status.is_ip = '1' AND
rx_hdr_status.is_udp = '1' AND
TO_UINT(rx_hdr_status.udp_port) = g_rx_udp_port THEN
rx_eth_discard <= '0'; -- pass on IP/UDP stream for g_rx_udp_port
END IF;
END IF;
rx_eth_discard_val <= rx_hdr_status_complete;
END IF;
END PROCESS;
END str;
......@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- AUthor: E. Kooistra
-- Purpose: Test bench for eth_stream using eth_tester
-- Purpose: Test bench for eth_stream_udp using eth_tester
-- Description:
-- Similar as tb_eth_tester.vhd, but for only one stream and using streaming
-- interface loop back.
......@@ -45,7 +45,7 @@ USE work.eth_pkg.ALL;
USE work.eth_tester_pkg.ALL;
USE work.tb_eth_tester_pkg.ALL;
ENTITY tb_eth_stream IS
ENTITY tb_eth_stream_udp IS
GENERIC (
g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
......@@ -62,10 +62,10 @@ ENTITY tb_eth_stream IS
-- nat: bsn_init
g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0) -- for first stream
);
END tb_eth_stream;
END tb_eth_stream_udp;
ARCHITECTURE tb OF tb_eth_stream IS
ARCHITECTURE tb OF tb_eth_stream_udp IS
CONSTANT c_tb_str : STRING := "tb-" & NATURAL'IMAGE(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
CONSTANT mm_clk_period : TIME := 10 ns; -- 100 MHz
......@@ -403,7 +403,7 @@ BEGIN
-- ETH stream
u_dut : ENTITY work.eth_stream
u_dut : ENTITY work.eth_stream_udp
GENERIC MAP (
g_rx_udp_port => c_rx_udp_port
)
......
......@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: E. Kooistra
-- Purpose: Multi test bench for eth_stream
-- Purpose: Multi test bench for eth_stream_udp
-- Description:
--
-- Usage:
......@@ -30,10 +30,10 @@ USE IEEE.std_logic_1164.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.tb_eth_tester_pkg.ALL;
ENTITY tb_tb_eth_stream IS
END tb_tb_eth_stream;
ENTITY tb_tb_eth_stream_udp IS
END tb_tb_eth_stream_udp;
ARCHITECTURE tb OF tb_tb_eth_stream IS
ARCHITECTURE tb OF tb_tb_eth_stream_udp IS
-- Tb
CONSTANT c_eth_clk_MHz : NATURAL := 125;
......@@ -74,7 +74,7 @@ BEGIN
-- -- nat: bsn_init
-- g_bg_ctrl : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0) -- for first stream
u_udp : ENTITY work.tb_eth_stream GENERIC MAP (0, c_nof_sync, TRUE, c_bg_ctrl);
u_udp_mismatch : ENTITY work.tb_eth_stream GENERIC MAP (1, c_nof_sync, FALSE, c_bg_ctrl);
u_udp : ENTITY work.tb_eth_stream_udp GENERIC MAP (0, c_nof_sync, TRUE, c_bg_ctrl);
u_udp_mismatch : ENTITY work.tb_eth_stream_udp GENERIC MAP (1, c_nof_sync, FALSE, c_bg_ctrl);
END tb;
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