Skip to content
Snippets Groups Projects
Commit bfb4ff16 authored by Daniel van der Schuur's avatar Daniel van der Schuur
Browse files

-Added a clock group for a second PLL in QSYS (used in unb1_correlator).

parent 1afdc2e7
No related branches found
No related tags found
No related merge requests found
......@@ -48,6 +48,9 @@ set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[
set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[2]]
set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[3]]
# QSYS, second PLL
set_clock_groups -asynchronous -group [get_clocks *|altpll_1|sd1|pll7|clk[0]]
set_clock_groups -asynchronous -group [get_clocks CLK]
set_clock_groups -asynchronous -group [get_clocks {*|altpll_component|auto_generated|pll1|clk[0]}]
set_clock_groups -asynchronous -group [get_clocks ADC_BI_A_CLK]
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment