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Commit 1afdc2e7 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Set the design constants to Apertif values; 

-Fixed data buffer depth;
-Set PLL output clock to 200MHz in QSYS;
-Validated on HW using tc_correlator.py.
parent 8d1db1ec
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applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
+ 44
− 44
View file @ 1afdc2e7
......@@ -52,14 +52,6 @@
type = "int";
}
}
element altpll_0.c0
{
datum _clockDomain
{
value = "mm_clk";
type = "String";
}
}
element c0
{
datum _sortIndex
......@@ -68,6 +60,14 @@
type = "int";
}
}
element altpll_0.c0
{
datum _clockDomain
{
value = "mm_clk";
type = "String";
}
}
element altpll_0.c1
{
datum _clockDomain
......@@ -121,7 +121,7 @@
type = "String";
}
}
element reg_diag_data_buf.mem
element ram_diag_data_buf.mem
{
datum baseAddress
{
......@@ -129,23 +129,23 @@
type = "long";
}
}
element ram_diag_data_buf.mem
element pio_pps.mem
{
datum baseAddress
{
value = "524288";
value = "328";
type = "long";
}
}
element pio_pps.mem
element reg_diag_data_buf.mem
{
datum baseAddress
{
value = "328";
value = "336";
type = "long";
}
}
element reg_wdi.mem
element pio_system_info.mem
{
datum _lockedAddress
{
......@@ -154,7 +154,7 @@
}
datum baseAddress
{
value = "12288";
value = "0";
type = "long";
}
}
......@@ -171,24 +171,24 @@
type = "long";
}
}
element reg_unb_sens.mem
element reg_wdi.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "224";
value = "12288";
type = "long";
}
}
element pio_system_info.mem
{
datum _lockedAddress
element reg_unb_sens.mem
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
value = "224";
type = "long";
}
}
......@@ -335,16 +335,11 @@
type = "int";
}
}
element onchip_memory2_0.s1
{
datum _lockedAddress
element pio_wdi.s1
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "131072";
value = "288";
type = "long";
}
}
......@@ -364,11 +359,16 @@
type = "long";
}
}
element pio_wdi.s1
element onchip_memory2_0.s1
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "288";
value = "131072";
type = "long";
}
}
......@@ -403,7 +403,7 @@
<parameter name="projectName" value="unb1_correlator.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1417186462108" />
<parameter name="timeStamp" value="1418396167104" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
......@@ -1370,7 +1370,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" />
<parameter name="dataAddrWidth" value="20" />
<parameter name="dataAddrWidth" value="18" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
......@@ -1380,7 +1380,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='altpll_1.pll_slave' start='0x130' end='0x140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x140' end='0x148' /><slave name='pio_pps.mem' start='0x148' end='0x150' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='reg_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buf.mem' start='0x80000' end='0x100000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='altpll_1.pll_slave' start='0x130' end='0x140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x140' end='0x148' /><slave name='pio_pps.mem' start='0x148' end='0x150' /><slave name='reg_diag_data_buf.mem' start='0x150' end='0x158' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
......@@ -1405,7 +1405,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="ram_diag_data_buf">
<parameter name="g_adr_w" value="17" />
<parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
......@@ -1414,7 +1414,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_diag_data_buf">
<parameter name="g_adr_w" value="10" />
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
......@@ -1451,7 +1451,7 @@ q]]></parameter>
<parameter name="DOWN_SPREAD" value="" />
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
<parameter name="CLK0_MULTIPLY_BY" value="5" />
<parameter name="CLK0_MULTIPLY_BY" value="1" />
<parameter name="CLK1_MULTIPLY_BY" value="" />
<parameter name="CLK2_MULTIPLY_BY" value="" />
<parameter name="CLK3_MULTIPLY_BY" value="" />
......@@ -1465,7 +1465,7 @@ q]]></parameter>
<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
<parameter name="CLK0_DIVIDE_BY" value="2" />
<parameter name="CLK0_DIVIDE_BY" value="1" />
<parameter name="CLK1_DIVIDE_BY" value="" />
<parameter name="CLK2_DIVIDE_BY" value="" />
<parameter name="CLK3_DIVIDE_BY" value="" />
......@@ -1575,8 +1575,8 @@ q]]></parameter>
<parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 5000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 200.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 500.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 500.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1417186481242185.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 5000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 200.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 200.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 200.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1417186481242185.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1</parameter>
<parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
......@@ -1933,7 +1933,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="ram_diag_data_buf.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00080000" />
<parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
......@@ -1941,7 +1941,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_data_buf.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x5000" />
<parameter name="baseAddress" value="0x0150" />
</connection>
<connection
kind="clock"
......
applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
+ 16
− 7
View file @ 1afdc2e7
......@@ -116,12 +116,14 @@ ARCHITECTURE str OF unb1_correlator IS
SIGNAL eth1g_ram_miso : t_mem_miso;
-- Correlator
CONSTANT c_nof_inputs : NATURAL := 10;
CONSTANT c_nof_pre_mult_folds : NATURAL := 4;
CONSTANT c_complex_data_w : NATURAL := 16;
CONSTANT c_nof_inputs : NATURAL := 24;
CONSTANT c_nof_pre_mult_folds : NATURAL := 1;
CONSTANT c_complex_data_w : NATURAL := 8;
CONSTANT c_conjugate : BOOLEAN := TRUE;
CONSTANT c_nof_channels : NATURAL := 64;
CONSTANT c_integration_period : NATURAL := 0;
CONSTANT c_integration_period : NATURAL := 12208;
CONSTANT c_nof_visibilities : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
-- Gap size on the correlator input depends on the number of folds
CONSTANT c_block_period : NATURAL := pow2(c_nof_pre_mult_folds);
......@@ -129,7 +131,14 @@ ARCHITECTURE str OF unb1_correlator IS
-- Block generator
CONSTANT c_bg_block_size : NATURAL := c_nof_channels;
CONSTANT c_bg_gapsize : NATURAL := c_bg_block_size*(c_block_period-1);
CONSTANT c_bg_blocks_per_sync : NATURAL := 10;
-- Indicate the integration period with the sync. In the correlator, the
-- integration period is forced to a minimum of c_nof_visibilities to
-- allow folding the output onto one stream.
-- . The sync pulse is only there for the human eye (wave window) -
-- it is not used by the correlator.
CONSTANT c_bg_blocks_per_sync : NATURAL := largest(c_integration_period, c_nof_visibilities);
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
......@@ -246,14 +255,14 @@ BEGIN
);
-----------------------------------------------------------------------------
-- Data buffers to be read out by Python
-- Data buffer to be read out by Python
-----------------------------------------------------------------------------
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => 1,
g_data_w => 64,
g_data_type => e_complex,
g_buf_nof_data => c_nof_channels,
g_buf_nof_data => c_nof_visibilities,
g_buf_use_sync => TRUE
)
PORT MAP (
......
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