From bfb4ff1604fd0854c7d91a51b3cd27ba4d267664 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Wed, 17 Dec 2014 07:23:59 +0000
Subject: [PATCH] -Added a clock group for a second PLL in QSYS (used in
unb1_correlator).
---
boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
index 312dc9f899..4a0102e430 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
@@ -48,6 +48,9 @@ set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[
set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[2]]
set_clock_groups -asynchronous -group [get_clocks *u_sopc|altpll_0|sd1|pll7|clk[3]]
+# QSYS, second PLL
+set_clock_groups -asynchronous -group [get_clocks *|altpll_1|sd1|pll7|clk[0]]
+
set_clock_groups -asynchronous -group [get_clocks CLK]
set_clock_groups -asynchronous -group [get_clocks {*|altpll_component|auto_generated|pll1|clk[0]}]
set_clock_groups -asynchronous -group [get_clocks ADC_BI_A_CLK]
--
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