diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index 9ce8b919d6ac56a60a36ebd6d9a9e313b95eb345..b95a8454fffb5d67dbe3aa17a1bd122ca2b5dc16 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index da74cab425657e1b1309118abf63a14e2ba1e214..e688dd3948effe51993c366bf847bd3d817e066e 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index 1200c599b55afd214a2cbb053835156adaa50eb0..43ce8e3667bd7f1258b3e6fd53fe3ac5f8dc74d4 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
index a487444ae83f4e0913e75aec64a29c442efff9ec..d548b22f664c3f22c5b600c2535e1135714ac74f 100644
--- a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),