From bcf1b2e3ee2398ab8cf9fcb10af4d8131baa4e9f Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 19 Dec 2022 15:34:29 +0100
Subject: [PATCH] corrected address width
---
libraries/technology/tse/tech_tse_arria10.vhd | 4 ++--
libraries/technology/tse/tech_tse_arria10_e1sg.vhd | 4 ++--
libraries/technology/tse/tech_tse_arria10_e2sg.vhd | 4 ++--
libraries/technology/tse/tech_tse_arria10_e3sge3.vhd | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index 9ce8b919d6..b95a8454ff 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index da74cab425..e688dd3948 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index 1200c599b5..43ce8e3667 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
index a487444ae8..d548b22f66 100644
--- a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
--
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