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Commit bb6a3256 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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update to quartus 14.1

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libraries/technology/ip_arria10/ddio/compile_ip.tcl
+ 7
− 7
View file @ bb6a3256
...@@ -29,10 +29,10 @@ if {$IPMODEL=="PHY"} { ...@@ -29,10 +29,10 @@ if {$IPMODEL=="PHY"} {
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/" set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists #vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_140 ./work/ vmap ip_arria10_ddio_in_1_altera_gpio_core_141 ./work/
vmap ip_arria10_ddio_out_1_altera_gpio_core_140 ./work/ vmap ip_arria10_ddio_out_1_altera_gpio_core_141 ./work/
vmap ip_arria10_ddio_in_1_altera_gpio_140 ./work/ vmap ip_arria10_ddio_in_1_altera_gpio_141 ./work/
vmap ip_arria10_ddio_out_1_altera_gpio_140 ./work/ vmap ip_arria10_ddio_out_1_altera_gpio_141 ./work/
# Quartus QIP uses the libraries, so map these here to work/ to be able to use these libraries also in simulation. # Quartus QIP uses the libraries, so map these here to work/ to be able to use these libraries also in simulation.
# However by instantiating the compenents as components instead of as entities it is not necessary to know the # However by instantiating the compenents as components instead of as entities it is not necessary to know the
...@@ -40,9 +40,9 @@ if {$IPMODEL=="PHY"} { ...@@ -40,9 +40,9 @@ if {$IPMODEL=="PHY"} {
#vmap ip_arria10_ddio_in_1 ./work/ #vmap ip_arria10_ddio_in_1 ./work/
#vmap ip_arria10_ddio_out_1 ./work/ #vmap ip_arria10_ddio_out_1 ./work/
vlog -sv "$IP_DIR/altera_gpio_core_140/sim/mentor/altera_gpio.sv" -work work vlog -sv "$IP_DIR/altera_gpio_core_141/sim/mentor/altera_gpio.sv" -work work
vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_in_1_altera_gpio_140_dtqjxiy.vhd" -work work vcom "$IP_DIR/altera_gpio_141/sim/ip_arria10_ddio_in_1_altera_gpio_141_hszcdqa.vhd" -work work
vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_out_1_altera_gpio_140_awilcdy.vhd" -work work vcom "$IP_DIR/altera_gpio_141/sim/ip_arria10_ddio_out_1_altera_gpio_141_edhgoly.vhd" -work work
vcom "$IP_DIR/sim/ip_arria10_ddio_in_1.vhd" vcom "$IP_DIR/sim/ip_arria10_ddio_in_1.vhd"
vcom "$IP_DIR/sim/ip_arria10_ddio_out_1.vhd" vcom "$IP_DIR/sim/ip_arria10_ddio_out_1.vhd"
......
libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
+ 38
− 32
View file @ bb6a3256
...@@ -11,6 +11,11 @@ ...@@ -11,6 +11,11 @@
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element ip_arria10_ddio_in_1 element ip_arria10_ddio_in_1
{ {
...@@ -23,9 +28,9 @@ ...@@ -23,9 +28,9 @@
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
...@@ -40,19 +45,6 @@ ...@@ -40,19 +45,6 @@
<parameter name="timeStamp" value="0" /> <parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface name="din" internal="ip_arria10_ddio_in_1.din" />
<interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
<interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
<interface
name="pad_in"
internal="ip_arria10_ddio_in_1.pad_in"
type="conduit"
dir="end">
<port name="datain" internal="datain" />
</interface>
<interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
<port name="inclock" internal="inclock" />
</interface>
<interface <interface
name="aclr" name="aclr"
internal="ip_arria10_ddio_in_1.aclr" internal="ip_arria10_ddio_in_1.aclr"
...@@ -60,6 +52,9 @@ ...@@ -60,6 +52,9 @@
dir="end"> dir="end">
<port name="aclr" internal="aclr" /> <port name="aclr" internal="aclr" />
</interface> </interface>
<interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
<port name="inclock" internal="inclock" />
</interface>
<interface <interface
name="dataout_h" name="dataout_h"
internal="ip_arria10_ddio_in_1.dataout_h" internal="ip_arria10_ddio_in_1.dataout_h"
...@@ -74,34 +69,45 @@ ...@@ -74,34 +69,45 @@
dir="end"> dir="end">
<port name="dataout_l" internal="dataout_l" /> <port name="dataout_l" internal="dataout_l" />
</interface> </interface>
<interface name="din" internal="ip_arria10_ddio_in_1.din" />
<interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
<interface
name="pad_in"
internal="ip_arria10_ddio_in_1.pad_in"
type="conduit"
dir="end">
<port name="datain" internal="datain" />
</interface>
<interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
<module <module
name="ip_arria10_ddio_in_1"
kind="altera_gpio" kind="altera_gpio"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="ip_arria10_ddio_in_1"
autoexport="1"> autoexport="1">
<parameter name="device_family" value="Arria 10" /> <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Input" /> <parameter name="PIN_TYPE_GUI" value="Input" />
<parameter name="SIZE" value="1" /> <parameter name="SIZE" value="1" />
<parameter name="gui_enable_migratable_port_names" value="true" /> <parameter name="device_family" value="Arria 10" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_use_oe" value="false" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_areset_mode" value="Clear" /> <parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" /> <parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" /> <parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" /> <parameter name="gui_separate_io_clks" value="false" />
<parameter name="EXT_DRIVER_PARAM" value="false" /> <parameter name="gui_sreset_mode" value="None" />
<parameter name="GENERATE_SDC_FILE" value="false" /> <parameter name="gui_use_oe" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
<parameter name="AUTO_DEVICE" value="Unknown" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
+ 39
− 29
View file @ bb6a3256
...@@ -11,6 +11,11 @@ ...@@ -11,6 +11,11 @@
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element ip_arria10_ddio_out_1 element ip_arria10_ddio_out_1
{ {
...@@ -23,9 +28,9 @@ ...@@ -23,9 +28,9 @@
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
...@@ -40,23 +45,19 @@ ...@@ -40,23 +45,19 @@
<parameter name="timeStamp" value="0" /> <parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface name="din" internal="ip_arria10_ddio_out_1.din" />
<interface <interface
name="pad_out" name="aclr"
internal="ip_arria10_ddio_out_1.pad_out" internal="ip_arria10_ddio_out_1.aclr"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="dataout" internal="dataout" /> <port name="aclr" internal="aclr" />
</interface>
<interface name="ck" internal="ip_arria10_ddio_out_1.ck" type="conduit" dir="end">
<port name="outclock" internal="outclock" />
</interface> </interface>
<interface <interface
name="aclr" name="ck"
internal="ip_arria10_ddio_out_1.aclr" internal="ip_arria10_ddio_out_1.ck"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="aclr" internal="aclr" /> <port name="outclock" internal="outclock" />
</interface> </interface>
<interface <interface
name="datain_h" name="datain_h"
...@@ -72,34 +73,43 @@ ...@@ -72,34 +73,43 @@
dir="end"> dir="end">
<port name="datain_l" internal="datain_l" /> <port name="datain_l" internal="datain_l" />
</interface> </interface>
<interface name="din" internal="ip_arria10_ddio_out_1.din" />
<interface
name="pad_out"
internal="ip_arria10_ddio_out_1.pad_out"
type="conduit"
dir="end">
<port name="dataout" internal="dataout" />
</interface>
<module <module
name="ip_arria10_ddio_out_1"
kind="altera_gpio" kind="altera_gpio"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="ip_arria10_ddio_out_1"
autoexport="1"> autoexport="1">
<parameter name="device_family" value="Arria 10" /> <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Output" /> <parameter name="PIN_TYPE_GUI" value="Output" />
<parameter name="SIZE" value="1" /> <parameter name="SIZE" value="1" />
<parameter name="gui_enable_migratable_port_names" value="true" /> <parameter name="device_family" value="Arria 10" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_use_oe" value="false" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_areset_mode" value="Clear" /> <parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" /> <parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" /> <parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" /> <parameter name="gui_separate_io_clks" value="false" />
<parameter name="EXT_DRIVER_PARAM" value="false" /> <parameter name="gui_sreset_mode" value="None" />
<parameter name="GENERATE_SDC_FILE" value="false" /> <parameter name="gui_use_oe" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
<parameter name="AUTO_DEVICE" value="Unknown" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
libraries/technology/ip_arria10/ddr4/ddr4.qsys
+ 584
− 478
View file @ bb6a3256
This diff is collapsed.
libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+ 91
− 91
View file @ bb6a3256
This diff is collapsed.
libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+ 1
− 1
View file @ bb6a3256
hdl_lib_name = ip_arria10_mac_10g hdl_lib_name = ip_arria10_mac_10g
hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_140 hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_141
hdl_lib_uses = hdl_lib_uses =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
......
libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
+ 121
− 114
View file @ bb6a3256
...@@ -11,6 +11,11 @@ ...@@ -11,6 +11,11 @@
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element alt_em10g32_0 element alt_em10g32_0
{ {
...@@ -23,9 +28,9 @@ ...@@ -23,9 +28,9 @@
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
...@@ -40,69 +45,36 @@ ...@@ -40,69 +45,36 @@
<parameter name="timeStamp" value="0" /> <parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
<port name="csr_read" internal="csr_read" />
<port name="csr_write" internal="csr_write" />
<port name="csr_writedata" internal="csr_writedata" />
<port name="csr_readdata" internal="csr_readdata" />
<port name="csr_waitrequest" internal="csr_waitrequest" />
<port name="csr_address" internal="csr_address" />
</interface>
<interface
name="tx_312_5_clk"
internal="alt_em10g32_0.tx_312_5_clk"
type="clock"
dir="end">
<port name="tx_312_5_clk" internal="tx_312_5_clk" />
</interface>
<interface
name="tx_156_25_clk"
internal="alt_em10g32_0.tx_156_25_clk"
type="clock"
dir="end">
<port name="tx_156_25_clk" internal="tx_156_25_clk" />
</interface>
<interface
name="rx_312_5_clk"
internal="alt_em10g32_0.rx_312_5_clk"
type="clock"
dir="end">
<port name="rx_312_5_clk" internal="rx_312_5_clk" />
</interface>
<interface
name="rx_156_25_clk"
internal="alt_em10g32_0.rx_156_25_clk"
type="clock"
dir="end">
<port name="rx_156_25_clk" internal="rx_156_25_clk" />
</interface>
<interface
name="csr_clk"
internal="alt_em10g32_0.csr_clk"
type="clock"
dir="end">
<port name="csr_clk" internal="csr_clk" />
</interface>
<interface <interface
name="csr_rst_n" name="avalon_st_pause"
internal="alt_em10g32_0.csr_rst_n" internal="alt_em10g32_0.avalon_st_pause"
type="reset" type="avalon_streaming"
dir="end"> dir="end">
<port name="csr_rst_n" internal="csr_rst_n" /> <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
</interface> </interface>
<interface <interface
name="tx_rst_n" name="avalon_st_rx"
internal="alt_em10g32_0.tx_rst_n" internal="alt_em10g32_0.avalon_st_rx"
type="reset" type="avalon_streaming"
dir="end"> dir="start">
<port name="tx_rst_n" internal="tx_rst_n" /> <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
<port
name="avalon_st_rx_startofpacket"
internal="avalon_st_rx_startofpacket" />
<port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
<port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
<port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
<port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
<port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
</interface> </interface>
<interface <interface
name="rx_rst_n" name="avalon_st_rxstatus"
internal="alt_em10g32_0.rx_rst_n" internal="alt_em10g32_0.avalon_st_rxstatus"
type="reset" type="avalon_streaming"
dir="end"> dir="start">
<port name="rx_rst_n" internal="rx_rst_n" /> <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
<port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
<port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
</interface> </interface>
<interface <interface
name="avalon_st_tx" name="avalon_st_tx"
...@@ -119,20 +91,6 @@ ...@@ -119,20 +91,6 @@
<port name="avalon_st_tx_error" internal="avalon_st_tx_error" /> <port name="avalon_st_tx_error" internal="avalon_st_tx_error" />
<port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" /> <port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" />
</interface> </interface>
<interface
name="avalon_st_pause"
internal="alt_em10g32_0.avalon_st_pause"
type="avalon_streaming"
dir="end">
<port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
</interface>
<interface
name="xgmii_tx"
internal="alt_em10g32_0.xgmii_tx"
type="avalon_streaming"
dir="start">
<port name="xgmii_tx" internal="xgmii_tx" />
</interface>
<interface <interface
name="avalon_st_txstatus" name="avalon_st_txstatus"
internal="alt_em10g32_0.avalon_st_txstatus" internal="alt_em10g32_0.avalon_st_txstatus"
...@@ -142,12 +100,27 @@ ...@@ -142,12 +100,27 @@
<port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" /> <port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" />
<port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" /> <port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" />
</interface> </interface>
<interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
<port name="csr_read" internal="csr_read" />
<port name="csr_write" internal="csr_write" />
<port name="csr_writedata" internal="csr_writedata" />
<port name="csr_readdata" internal="csr_readdata" />
<port name="csr_waitrequest" internal="csr_waitrequest" />
<port name="csr_address" internal="csr_address" />
</interface>
<interface <interface
name="xgmii_rx" name="csr_clk"
internal="alt_em10g32_0.xgmii_rx" internal="alt_em10g32_0.csr_clk"
type="avalon_streaming" type="clock"
dir="end"> dir="end">
<port name="xgmii_rx" internal="xgmii_rx" /> <port name="csr_clk" internal="csr_clk" />
</interface>
<interface
name="csr_rst_n"
internal="alt_em10g32_0.csr_rst_n"
type="reset"
dir="end">
<port name="csr_rst_n" internal="csr_rst_n" />
</interface> </interface>
<interface <interface
name="link_fault_status_xgmii_rx" name="link_fault_status_xgmii_rx"
...@@ -159,28 +132,46 @@ ...@@ -159,28 +132,46 @@
internal="link_fault_status_xgmii_rx_data" /> internal="link_fault_status_xgmii_rx_data" />
</interface> </interface>
<interface <interface
name="avalon_st_rx" name="rx_156_25_clk"
internal="alt_em10g32_0.avalon_st_rx" internal="alt_em10g32_0.rx_156_25_clk"
type="avalon_streaming" type="clock"
dir="start"> dir="end">
<port name="avalon_st_rx_data" internal="avalon_st_rx_data" /> <port name="rx_156_25_clk" internal="rx_156_25_clk" />
<port
name="avalon_st_rx_startofpacket"
internal="avalon_st_rx_startofpacket" />
<port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
<port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
<port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
<port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
<port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
</interface> </interface>
<interface <interface
name="avalon_st_rxstatus" name="rx_312_5_clk"
internal="alt_em10g32_0.avalon_st_rxstatus" internal="alt_em10g32_0.rx_312_5_clk"
type="avalon_streaming" type="clock"
dir="start"> dir="end">
<port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" /> <port name="rx_312_5_clk" internal="rx_312_5_clk" />
<port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" /> </interface>
<port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" /> <interface
name="rx_rst_n"
internal="alt_em10g32_0.rx_rst_n"
type="reset"
dir="end">
<port name="rx_rst_n" internal="rx_rst_n" />
</interface>
<interface
name="tx_156_25_clk"
internal="alt_em10g32_0.tx_156_25_clk"
type="clock"
dir="end">
<port name="tx_156_25_clk" internal="tx_156_25_clk" />
</interface>
<interface
name="tx_312_5_clk"
internal="alt_em10g32_0.tx_312_5_clk"
type="clock"
dir="end">
<port name="tx_312_5_clk" internal="tx_312_5_clk" />
</interface>
<interface
name="tx_rst_n"
internal="alt_em10g32_0.tx_rst_n"
type="reset"
dir="end">
<port name="tx_rst_n" internal="tx_rst_n" />
</interface> </interface>
<interface <interface
name="unidirectional" name="unidirectional"
...@@ -192,35 +183,51 @@ ...@@ -192,35 +183,51 @@
name="unidirectional_remote_fault_dis" name="unidirectional_remote_fault_dis"
internal="unidirectional_remote_fault_dis" /> internal="unidirectional_remote_fault_dis" />
</interface> </interface>
<interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" /> <interface
<interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" /> name="xgmii_rx"
<interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" /> internal="alt_em10g32_0.xgmii_rx"
type="avalon_streaming"
dir="end">
<port name="xgmii_rx" internal="xgmii_rx" />
</interface>
<interface name="xgmii_rx_control" internal="alt_em10g32_0.xgmii_rx_control" /> <interface name="xgmii_rx_control" internal="alt_em10g32_0.xgmii_rx_control" />
<interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" />
<interface
name="xgmii_tx"
internal="alt_em10g32_0.xgmii_tx"
type="avalon_streaming"
dir="start">
<port name="xgmii_tx" internal="xgmii_tx" />
</interface>
<interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" />
<interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" />
<module <module
name="alt_em10g32_0"
kind="alt_em10g32" kind="alt_em10g32"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="alt_em10g32_0"
autoexport="1"> autoexport="1">
<parameter name="DATAPATH_OPTION" value="3" />
<parameter name="DEVICE_FAMILY" value="Arria 10" /> <parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="INSERT_ST_ADAPTOR" value="1" /> <parameter name="ENABLE_10GBASER_REG_MODE" value="0" />
<parameter name="ENABLE_1G10G_MAC" value="0" />
<parameter name="ENABLE_MEM_ECC" value="0" />
<parameter name="ENABLE_PFC" value="0" />
<parameter name="ENABLE_PTP_1STEP" value="0" />
<parameter name="ENABLE_SUPP_ADDR" value="0" />
<parameter name="ENABLE_TIMESTAMPING" value="0" />
<parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
<parameter name="INSERT_CSR_ADAPTOR" value="1" /> <parameter name="INSERT_CSR_ADAPTOR" value="1" />
<parameter name="INSERT_ST_ADAPTOR" value="1" />
<parameter name="INSERT_XGMII_ADAPTOR" value="1" /> <parameter name="INSERT_XGMII_ADAPTOR" value="1" />
<parameter name="DATAPATH_OPTION" value="3" />
<parameter name="ENABLE_SUPP_ADDR" value="0" />
<parameter name="ENABLE_PFC" value="0" />
<parameter name="PFC_PRIORITY_NUMBER" value="8" />
<parameter name="INSTANTIATE_STATISTICS" value="0" /> <parameter name="INSTANTIATE_STATISTICS" value="0" />
<parameter name="REGISTER_BASED_STATISTICS" value="0" /> <parameter name="PFC_PRIORITY_NUMBER" value="8" />
<parameter name="PREAMBLE_PASSTHROUGH" value="0" /> <parameter name="PREAMBLE_PASSTHROUGH" value="0" />
<parameter name="ENABLE_TIMESTAMPING" value="0" /> <parameter name="REGISTER_BASED_STATISTICS" value="0" />
<parameter name="ENABLE_PTP_1STEP" value="0" /> <parameter name="TIME_OF_DAY_FORMAT" value="2" />
<parameter name="TSTAMP_FP_WIDTH" value="4" /> <parameter name="TSTAMP_FP_WIDTH" value="4" />
<parameter name="ENABLE_1G10G_MAC" value="0" />
<parameter name="ENABLE_MEM_ECC" value="0" />
<parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+ 1
− 1
View file @ bb6a3256
hdl_lib_name = ip_arria10_phy_10gbase_r hdl_lib_name = ip_arria10_phy_10gbase_r
hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140 hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
hdl_lib_uses = hdl_lib_uses =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
......
libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
+ 80
− 76
View file @ bb6a3256
...@@ -6,19 +6,29 @@ ...@@ -6,19 +6,29 @@
version="1.0" version="1.0"
description="" description=""
tags="INTERNAL_COMPONENT=true" tags="INTERNAL_COMPONENT=true"
categories="" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element transceiver_pll_inst element transceiver_pll_inst
{ {
datum _sortIndex
{
value = "0";
type = "int";
}
} }
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U3F45I2SGES" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
...@@ -36,18 +46,25 @@ ...@@ -36,18 +46,25 @@
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface <interface
name="pll_powerdown" name="mcgb_rst"
internal="transceiver_pll_inst.pll_powerdown" internal="transceiver_pll_inst.mcgb_rst"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="pll_powerdown" internal="pll_powerdown" /> <port name="mcgb_rst" internal="mcgb_rst" />
</interface> </interface>
<interface <interface
name="pll_refclk0" name="mcgb_serial_clk"
internal="transceiver_pll_inst.pll_refclk0" internal="transceiver_pll_inst.mcgb_serial_clk"
type="clock" type="hssi_serial_clock"
dir="start">
<port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
</interface>
<interface
name="pll_cal_busy"
internal="transceiver_pll_inst.pll_cal_busy"
type="conduit"
dir="end"> dir="end">
<port name="pll_refclk0" internal="pll_refclk0" /> <port name="pll_cal_busy" internal="pll_cal_busy" />
</interface> </interface>
<interface <interface
name="pll_locked" name="pll_locked"
...@@ -57,98 +74,85 @@ ...@@ -57,98 +74,85 @@
<port name="pll_locked" internal="pll_locked" /> <port name="pll_locked" internal="pll_locked" />
</interface> </interface>
<interface <interface
name="pll_cal_busy" name="pll_powerdown"
internal="transceiver_pll_inst.pll_cal_busy" internal="transceiver_pll_inst.pll_powerdown"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" /> <port name="pll_powerdown" internal="pll_powerdown" />
</interface> </interface>
<interface <interface
name="mcgb_rst" name="pll_refclk0"
internal="transceiver_pll_inst.mcgb_rst" internal="transceiver_pll_inst.pll_refclk0"
type="conduit" type="clock"
dir="end"> dir="end">
<port name="mcgb_rst" internal="mcgb_rst" /> <port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<interface
name="mcgb_serial_clk"
internal="transceiver_pll_inst.mcgb_serial_clk"
type="hssi_serial_clock"
dir="start">
<port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
</interface> </interface>
<module <module
name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10" kind="altera_xcvr_atx_pll_a10"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="transceiver_pll_inst"
autoexport="1"> autoexport="1">
<parameter name="rcfg_debug" value="0" /> <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="low" />
<parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_mcgb" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" /> <parameter name="enable_pll_reconfig" value="0" />
<parameter name="rcfg_jtag_enable" value="0" /> <parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="set_embedded_debug_enable" value="0" /> <parameter name="generate_docs" value="1" />
<parameter name="set_capability_reg_enable" value="0" /> <parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="set_user_identifier" value="0" /> <parameter name="mcgb_div" value="1" />
<parameter name="set_csr_soft_logic_enable" value="0" /> <parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter> <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" /> <parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" /> <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" /> <parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" /> <parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" /> <parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" /> <parameter name="rcfg_param_vals2" value="" />
<parameter name="generate_docs" value="1" /> <parameter name="rcfg_profile_cnt" value="2" />
<parameter name="generate_add_hdl_instance_example" value="0" /> <parameter name="rcfg_profile_select" value="1" />
<parameter name="device_family" value="Arria 10" /> <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="device" value="10AX115U3F45I2SGES" /> <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="test_mode" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="support_mode" value="user_mode" />
<parameter name="message_level" value="error" />
<parameter name="prot_mode" value="Basic" />
<parameter name="bw_sel" value="low" />
<parameter name="refclk_cnt" value="1" /> <parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" /> <parameter name="refclk_index" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="enable_8G_path" value="0" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="select_manual_config" value="0" /> <parameter name="select_manual_config" value="0" />
<parameter name="set_output_clock_frequency" value="5156.25" /> <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="enable_fractional" value="0" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" /> <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" /> <parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" /> <parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" /> <parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
<parameter name="set_output_clock_frequency" value="5156.25" />
<parameter name="set_ref_clk_div" value="1" /> <parameter name="set_ref_clk_div" value="1" />
<parameter name="set_l_counter" value="2" /> <parameter name="set_user_identifier" value="0" />
<parameter name="set_k_counter" value="1" /> <parameter name="silicon_rev" value="false" />
<parameter name="enable_mcgb" value="1" /> <parameter name="support_mode" value="user_mode" />
<parameter name="mcgb_div" value="1" /> <parameter name="test_mode" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="pma_width" value="64" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+ 17
− 17
View file @ bb6a3256
...@@ -30,22 +30,22 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g ...@@ -30,22 +30,22 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g
#vlib ./work/ ;# Assume library work already exists #vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 ./work/ vmap ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vcom "$IP_DIR/ip_arria10_transceiver_pll_10g.vhd" vcom "$IP_DIR/ip_arria10_transceiver_pll_10g.vhd"
libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+ 1
− 1
View file @ bb6a3256
hdl_lib_name = ip_arria10_transceiver_pll_10g hdl_lib_name = ip_arria10_transceiver_pll_10g
hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
hdl_lib_uses = hdl_lib_uses =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
......
libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
+ 69
− 70
View file @ bb6a3256
...@@ -6,11 +6,16 @@ ...@@ -6,11 +6,16 @@
version="1.0" version="1.0"
description="" description=""
tags="INTERNAL_COMPONENT=true" tags="INTERNAL_COMPONENT=true"
categories="" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element xcvr_atx_pll_a10_0 element xcvr_atx_pll_a10_0
{ {
...@@ -23,9 +28,9 @@ ...@@ -23,9 +28,9 @@
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
...@@ -40,6 +45,20 @@ ...@@ -40,6 +45,20 @@
<parameter name="timeStamp" value="0" /> <parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface
name="pll_cal_busy"
internal="xcvr_atx_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
internal="xcvr_atx_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface <interface
name="pll_powerdown" name="pll_powerdown"
internal="xcvr_atx_pll_a10_0.pll_powerdown" internal="xcvr_atx_pll_a10_0.pll_powerdown"
...@@ -61,92 +80,72 @@ ...@@ -61,92 +80,72 @@
dir="start"> dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" /> <port name="tx_serial_clk" internal="tx_serial_clk" />
</interface> </interface>
<interface
name="pll_locked"
internal="xcvr_atx_pll_a10_0.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_cal_busy"
internal="xcvr_atx_pll_a10_0.pll_cal_busy"
type="conduit"
dir="end">
<port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<module <module
name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10" kind="altera_xcvr_atx_pll_a10"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="xcvr_atx_pll_a10_0"
autoexport="1"> autoexport="1">
<parameter name="rcfg_debug" value="0" /> <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="low" />
<parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_mcgb" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" /> <parameter name="enable_pll_reconfig" value="0" />
<parameter name="rcfg_jtag_enable" value="0" /> <parameter name="generate_add_hdl_instance_example" value="0" />
<parameter name="set_embedded_debug_enable" value="0" /> <parameter name="generate_docs" value="1" />
<parameter name="set_capability_reg_enable" value="0" /> <parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="set_user_identifier" value="0" /> <parameter name="mcgb_div" value="1" />
<parameter name="set_csr_soft_logic_enable" value="0" /> <parameter name="message_level" value="error" />
<parameter name="pma_width" value="64" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter> <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" /> <parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" /> <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" /> <parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" /> <parameter name="rcfg_multi_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" /> <parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" /> <parameter name="rcfg_param_vals2" value="" />
<parameter name="generate_docs" value="1" /> <parameter name="rcfg_profile_cnt" value="2" />
<parameter name="generate_add_hdl_instance_example" value="0" /> <parameter name="rcfg_profile_select" value="1" />
<parameter name="device_family" value="Arria 10" /> <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="device" value="Unknown" /> <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="test_mode" value="0" />
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
<parameter name="enable_debug_ports_parameters" value="0" />
<parameter name="support_mode" value="user_mode" />
<parameter name="message_level" value="error" />
<parameter name="prot_mode" value="Basic" />
<parameter name="bw_sel" value="low" />
<parameter name="refclk_cnt" value="1" /> <parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" /> <parameter name="refclk_index" value="0" />
<parameter name="silicon_rev" value="false" />
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_pcie_clk" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="select_manual_config" value="0" /> <parameter name="select_manual_config" value="0" />
<parameter name="set_output_clock_frequency" value="5156.25" /> <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="enable_fractional" value="0" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" /> <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" /> <parameter name="set_capability_reg_enable" value="0" />
<parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" /> <parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" /> <parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
<parameter name="set_output_clock_frequency" value="5156.25" />
<parameter name="set_ref_clk_div" value="1" /> <parameter name="set_ref_clk_div" value="1" />
<parameter name="set_l_counter" value="2" /> <parameter name="set_user_identifier" value="0" />
<parameter name="set_k_counter" value="1" /> <parameter name="silicon_rev" value="false" />
<parameter name="enable_mcgb" value="0" /> <parameter name="support_mode" value="user_mode" />
<parameter name="mcgb_div" value="1" /> <parameter name="test_mode" value="0" />
<parameter name="enable_hfreq_clk" value="0" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="mcgb_aux_clkin_cnt" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_fb_comp_bonding" value="0" />
<parameter name="pma_width" value="64" />
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="0" />
<parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
<parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
<parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+ 9
− 9
View file @ bb6a3256
...@@ -30,14 +30,14 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_c ...@@ -30,14 +30,14 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_c
#vlib ./work/ ;# Assume library work already exists #vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 ./work/ vmap ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vcom "$IP_DIR/ip_arria10_transceiver_reset_controller_1.vhd" vcom "$IP_DIR/ip_arria10_transceiver_reset_controller_1.vhd"
libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+ 1
− 1
View file @ bb6a3256
hdl_lib_name = ip_arria10_transceiver_reset_controller_1 hdl_lib_name = ip_arria10_transceiver_reset_controller_1
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
hdl_lib_uses = hdl_lib_uses =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
......
libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
+ 60
− 54
View file @ bb6a3256
...@@ -11,6 +11,11 @@ ...@@ -11,6 +11,11 @@
{ {
element $${FILENAME} element $${FILENAME}
{ {
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
} }
element xcvr_reset_control_0 element xcvr_reset_control_0
{ {
...@@ -23,9 +28,9 @@ ...@@ -23,9 +28,9 @@
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" /> <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" /> <parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" /> <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
...@@ -48,11 +53,11 @@ ...@@ -48,11 +53,11 @@
<port name="clock" internal="clock" /> <port name="clock" internal="clock" />
</interface> </interface>
<interface <interface
name="reset" name="pll_locked"
internal="xcvr_reset_control_0.reset" internal="xcvr_reset_control_0.pll_locked"
type="reset" type="conduit"
dir="end"> dir="end">
<port name="reset" internal="reset" /> <port name="pll_locked" internal="pll_locked" />
</interface> </interface>
<interface <interface
name="pll_powerdown" name="pll_powerdown"
...@@ -62,110 +67,111 @@ ...@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" /> <port name="pll_powerdown" internal="pll_powerdown" />
</interface> </interface>
<interface <interface
name="tx_analogreset" name="pll_select"
internal="xcvr_reset_control_0.tx_analogreset" internal="xcvr_reset_control_0.pll_select"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="tx_analogreset" internal="tx_analogreset" /> <port name="pll_select" internal="pll_select" />
</interface> </interface>
<interface <interface
name="tx_digitalreset" name="reset"
internal="xcvr_reset_control_0.tx_digitalreset" internal="xcvr_reset_control_0.reset"
type="conduit" type="reset"
dir="end"> dir="end">
<port name="tx_digitalreset" internal="tx_digitalreset" /> <port name="reset" internal="reset" />
</interface> </interface>
<interface <interface
name="tx_ready" name="rx_analogreset"
internal="xcvr_reset_control_0.tx_ready" internal="xcvr_reset_control_0.rx_analogreset"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="tx_ready" internal="tx_ready" /> <port name="rx_analogreset" internal="rx_analogreset" />
</interface> </interface>
<interface <interface
name="pll_locked" name="rx_cal_busy"
internal="xcvr_reset_control_0.pll_locked" internal="xcvr_reset_control_0.rx_cal_busy"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="pll_locked" internal="pll_locked" /> <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface> </interface>
<interface <interface
name="pll_select" name="rx_digitalreset"
internal="xcvr_reset_control_0.pll_select" internal="xcvr_reset_control_0.rx_digitalreset"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="pll_select" internal="pll_select" /> <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface> </interface>
<interface <interface
name="tx_cal_busy" name="rx_is_lockedtodata"
internal="xcvr_reset_control_0.tx_cal_busy" internal="xcvr_reset_control_0.rx_is_lockedtodata"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="tx_cal_busy" internal="tx_cal_busy" /> <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface> </interface>
<interface <interface
name="rx_analogreset" name="rx_ready"
internal="xcvr_reset_control_0.rx_analogreset" internal="xcvr_reset_control_0.rx_ready"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="rx_analogreset" internal="rx_analogreset" /> <port name="rx_ready" internal="rx_ready" />
</interface> </interface>
<interface <interface
name="rx_digitalreset" name="tx_analogreset"
internal="xcvr_reset_control_0.rx_digitalreset" internal="xcvr_reset_control_0.tx_analogreset"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="rx_digitalreset" internal="rx_digitalreset" /> <port name="tx_analogreset" internal="tx_analogreset" />
</interface> </interface>
<interface <interface
name="rx_ready" name="tx_cal_busy"
internal="xcvr_reset_control_0.rx_ready" internal="xcvr_reset_control_0.tx_cal_busy"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="rx_ready" internal="rx_ready" /> <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface> </interface>
<interface <interface
name="rx_is_lockedtodata" name="tx_digitalreset"
internal="xcvr_reset_control_0.rx_is_lockedtodata" internal="xcvr_reset_control_0.tx_digitalreset"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" /> <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface> </interface>
<interface <interface
name="rx_cal_busy" name="tx_ready"
internal="xcvr_reset_control_0.rx_cal_busy" internal="xcvr_reset_control_0.tx_ready"
type="conduit" type="conduit"
dir="end"> dir="end">
<port name="rx_cal_busy" internal="rx_cal_busy" /> <port name="tx_ready" internal="tx_ready" />
</interface> </interface>
<module <module
name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control" kind="altera_xcvr_reset_control"
version="14.0" version="14.1"
enabled="1" enabled="1"
name="xcvr_reset_control_0"
autoexport="1"> autoexport="1">
<parameter name="CHANNELS" value="1" /> <parameter name="CHANNELS" value="1" />
<parameter name="PLLS" value="1" /> <parameter name="PLLS" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="156" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="0" /> <parameter name="REDUCED_SIM_TIME" value="0" />
<parameter name="gui_split_interfaces" value="0" /> <parameter name="RX_ENABLE" value="1" />
<parameter name="TX_PLL_ENABLE" value="1" /> <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" /> <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="156" />
<parameter name="TX_ENABLE" value="1" /> <parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" /> <parameter name="TX_PER_CHANNEL" value="0" />
<parameter name="gui_tx_auto_reset" value="1" /> <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="T_PLL_LOCK_HYST" value="0" /> <parameter name="T_PLL_LOCK_HYST" value="0" />
<parameter name="RX_ENABLE" value="1" /> <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="gui_rx_auto_reset" value="0" />
<parameter name="T_RX_ANALOGRESET" value="40" /> <parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" /> <parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" /> <parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="0" />
<parameter name="gui_rx_auto_reset" value="0" />
<parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="1" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system> </system>
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