diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index f639806b000da0153d4c7555702f06611e4428ce..2738f3eb21513fc647515c4c39577e2144466c45 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -29,10 +29,10 @@ if {$IPMODEL=="PHY"} {
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/"
#vlib ./work/ ;# Assume library work already exists
- vmap ip_arria10_ddio_in_1_altera_gpio_core_140 ./work/
- vmap ip_arria10_ddio_out_1_altera_gpio_core_140 ./work/
- vmap ip_arria10_ddio_in_1_altera_gpio_140 ./work/
- vmap ip_arria10_ddio_out_1_altera_gpio_140 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_core_141 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_core_141 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_141 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_141 ./work/
# Quartus QIP uses the libraries, so map these here to work/ to be able to use these libraries also in simulation.
# However by instantiating the compenents as components instead of as entities it is not necessary to know the
@@ -40,9 +40,9 @@ if {$IPMODEL=="PHY"} {
#vmap ip_arria10_ddio_in_1 ./work/
#vmap ip_arria10_ddio_out_1 ./work/
- vlog -sv "$IP_DIR/altera_gpio_core_140/sim/mentor/altera_gpio.sv" -work work
- vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_in_1_altera_gpio_140_dtqjxiy.vhd" -work work
- vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_out_1_altera_gpio_140_awilcdy.vhd" -work work
+ vlog -sv "$IP_DIR/altera_gpio_core_141/sim/mentor/altera_gpio.sv" -work work
+ vcom "$IP_DIR/altera_gpio_141/sim/ip_arria10_ddio_in_1_altera_gpio_141_hszcdqa.vhd" -work work
+ vcom "$IP_DIR/altera_gpio_141/sim/ip_arria10_ddio_out_1_altera_gpio_141_edhgoly.vhd" -work work
vcom "$IP_DIR/sim/ip_arria10_ddio_in_1.vhd"
vcom "$IP_DIR/sim/ip_arria10_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
index 58e7e3a5de8e40caf7f5bc730b9a2b8879b36bfa..d0bff52de404c9f41ca4b129fa208408d0da1c68 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element ip_arria10_ddio_in_1
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -40,19 +45,6 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
- <interface name="din" internal="ip_arria10_ddio_in_1.din" />
- <interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
- <interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
- <interface
- name="pad_in"
- internal="ip_arria10_ddio_in_1.pad_in"
- type="conduit"
- dir="end">
- <port name="datain" internal="datain" />
- </interface>
- <interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
- <port name="inclock" internal="inclock" />
- </interface>
<interface
name="aclr"
internal="ip_arria10_ddio_in_1.aclr"
@@ -60,6 +52,9 @@
dir="end">
<port name="aclr" internal="aclr" />
</interface>
+ <interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
+ <port name="inclock" internal="inclock" />
+ </interface>
<interface
name="dataout_h"
internal="ip_arria10_ddio_in_1.dataout_h"
@@ -74,34 +69,45 @@
dir="end">
<port name="dataout_l" internal="dataout_l" />
</interface>
+ <interface name="din" internal="ip_arria10_ddio_in_1.din" />
+ <interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
+ <interface
+ name="pad_in"
+ internal="ip_arria10_ddio_in_1.pad_in"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
<module
+ name="ip_arria10_ddio_in_1"
kind="altera_gpio"
- version="14.0"
+ version="14.1"
enabled="1"
- name="ip_arria10_ddio_in_1"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Input" />
<parameter name="SIZE" value="1" />
- <parameter name="gui_enable_migratable_port_names" value="true" />
- <parameter name="gui_diff_buff" value="false" />
- <parameter name="gui_pseudo_diff" value="false" />
- <parameter name="gui_bus_hold" value="false" />
- <parameter name="gui_open_drain" value="false" />
- <parameter name="gui_use_oe" value="false" />
- <parameter name="gui_enable_termination_ports" value="false" />
- <parameter name="gui_io_reg_mode" value="DDIO" />
- <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
- <parameter name="EXT_DRIVER_PARAM" value="false" />
- <parameter name="GENERATE_SDC_FILE" value="false" />
- <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
- <parameter name="AUTO_DEVICE" value="Unknown" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
index f06b7fff7875ee9ff5584500535d64f58f25c0c8..b312c320ff1f23cf150ea0a25f6e5111cf367e0a 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element ip_arria10_ddio_out_1
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -40,23 +45,19 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
- <interface name="din" internal="ip_arria10_ddio_out_1.din" />
<interface
- name="pad_out"
- internal="ip_arria10_ddio_out_1.pad_out"
+ name="aclr"
+ internal="ip_arria10_ddio_out_1.aclr"
type="conduit"
dir="end">
- <port name="dataout" internal="dataout" />
- </interface>
- <interface name="ck" internal="ip_arria10_ddio_out_1.ck" type="conduit" dir="end">
- <port name="outclock" internal="outclock" />
+ <port name="aclr" internal="aclr" />
</interface>
<interface
- name="aclr"
- internal="ip_arria10_ddio_out_1.aclr"
+ name="ck"
+ internal="ip_arria10_ddio_out_1.ck"
type="conduit"
dir="end">
- <port name="aclr" internal="aclr" />
+ <port name="outclock" internal="outclock" />
</interface>
<interface
name="datain_h"
@@ -72,34 +73,43 @@
dir="end">
<port name="datain_l" internal="datain_l" />
</interface>
+ <interface name="din" internal="ip_arria10_ddio_out_1.din" />
+ <interface
+ name="pad_out"
+ internal="ip_arria10_ddio_out_1.pad_out"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
<module
+ name="ip_arria10_ddio_out_1"
kind="altera_gpio"
- version="14.0"
+ version="14.1"
enabled="1"
- name="ip_arria10_ddio_out_1"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Output" />
<parameter name="SIZE" value="1" />
- <parameter name="gui_enable_migratable_port_names" value="true" />
- <parameter name="gui_diff_buff" value="false" />
- <parameter name="gui_pseudo_diff" value="false" />
- <parameter name="gui_bus_hold" value="false" />
- <parameter name="gui_open_drain" value="false" />
- <parameter name="gui_use_oe" value="false" />
- <parameter name="gui_enable_termination_ports" value="false" />
- <parameter name="gui_io_reg_mode" value="DDIO" />
- <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
- <parameter name="EXT_DRIVER_PARAM" value="false" />
- <parameter name="GENERATE_SDC_FILE" value="false" />
- <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
- <parameter name="AUTO_DEVICE" value="Unknown" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/ddr4/ddr4.qsys b/libraries/technology/ip_arria10/ddr4/ddr4.qsys
index 77341b0b94ad6494ac51e65a81c23c84873bb54b..72e82713e68bda046a97f1939687e5d033b20426 100644
--- a/libraries/technology/ip_arria10/ddr4/ddr4.qsys
+++ b/libraries/technology/ip_arria10/ddr4/ddr4.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element ddr4_inst
{
@@ -23,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@@ -41,25 +46,40 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="global_reset_reset_sink"
- internal="ddr4_inst.global_reset_reset_sink"
- type="reset"
+ name="ctrl_amm_avalon_slave_0"
+ internal="ddr4_inst.ctrl_amm_avalon_slave_0"
+ type="avalon"
dir="end">
- <port name="global_reset_n" internal="global_reset_n" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
</interface>
<interface
- name="pll_ref_clk_clock_sink"
- internal="ddr4_inst.pll_ref_clk_clock_sink"
+ name="emif_usr_clk_clock_source"
+ internal="ddr4_inst.emif_usr_clk_clock_source"
type="clock"
- dir="end">
- <port name="pll_ref_clk" internal="pll_ref_clk" />
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
</interface>
<interface
- name="oct_conduit_end"
- internal="ddr4_inst.oct_conduit_end"
- type="conduit"
+ name="emif_usr_reset_reset_source"
+ internal="ddr4_inst.emif_usr_reset_reset_source"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_reset_sink"
+ internal="ddr4_inst.global_reset_reset_sink"
+ type="reset"
dir="end">
- <port name="oct_rzqin" internal="oct_rzqin" />
+ <port name="global_reset_n" internal="global_reset_n" />
</interface>
<interface
name="mem_conduit_end"
@@ -84,573 +104,659 @@
<port name="mem_dbi_n" internal="mem_dbi_n" />
</interface>
<interface
- name="status_conduit_end"
- internal="ddr4_inst.status_conduit_end"
+ name="oct_conduit_end"
+ internal="ddr4_inst.oct_conduit_end"
type="conduit"
dir="end">
- <port name="local_cal_success" internal="local_cal_success" />
- <port name="local_cal_fail" internal="local_cal_fail" />
- </interface>
- <interface
- name="emif_usr_reset_reset_source"
- internal="ddr4_inst.emif_usr_reset_reset_source"
- type="reset"
- dir="start">
- <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ <port name="oct_rzqin" internal="oct_rzqin" />
</interface>
<interface
- name="emif_usr_clk_clock_source"
- internal="ddr4_inst.emif_usr_clk_clock_source"
+ name="pll_ref_clk_clock_sink"
+ internal="ddr4_inst.pll_ref_clk_clock_sink"
type="clock"
- dir="start">
- <port name="emif_usr_clk" internal="emif_usr_clk" />
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
</interface>
<interface
- name="ctrl_amm_avalon_slave_0"
- internal="ddr4_inst.ctrl_amm_avalon_slave_0"
- type="avalon"
+ name="status_conduit_end"
+ internal="ddr4_inst.status_conduit_end"
+ type="conduit"
dir="end">
- <port name="amm_ready_0" internal="amm_ready_0" />
- <port name="amm_read_0" internal="amm_read_0" />
- <port name="amm_write_0" internal="amm_write_0" />
- <port name="amm_address_0" internal="amm_address_0" />
- <port name="amm_readdata_0" internal="amm_readdata_0" />
- <port name="amm_writedata_0" internal="amm_writedata_0" />
- <port name="amm_burstcount_0" internal="amm_burstcount_0" />
- <port name="amm_byteenable_0" internal="amm_byteenable_0" />
- <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ <port name="local_cal_fail" internal="local_cal_fail" />
</interface>
<module
+ name="ddr4_inst"
kind="altera_emif"
- version="14.0"
+ version="14.1"
enabled="1"
- name="ddr4_inst"
autoexport="1">
- <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45I2SGES" />
- <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
- <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
<parameter name="INTERNAL_TESTING_MODE" value="false" />
- <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
- <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
- <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
- <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
- <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
- <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
- <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
- <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
- <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
- <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
- <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
- <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
- <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
- <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
- <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
- <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
- <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
- <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
- <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
- <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
- <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
- <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
- <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
- <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
- <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
- <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
- <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
- <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
- <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
- <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
- <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
<parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
<parameter name="MEM_DDR3_CK_WIDTH" value="1" />
- <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
<parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
- <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
<parameter name="MEM_DDR3_DM_EN" value="true" />
- <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
- <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
<parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
- <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
- <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
- <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
- <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
- <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
- <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
<parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
- <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
- <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
<parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
<parameter name="MEM_DDR3_RTT_WR_ENUM">DDR3_RTT_WR_ODT_DISABLED</parameter>
- <parameter name="MEM_DDR3_WTCL" value="6" />
- <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
- <parameter name="MEM_DDR3_TCL" value="7" />
- <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
- <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
<parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
- <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
- <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
- <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
<parameter name="MEM_DDR3_R_ODT0_2X2" value="off,on" />
- <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
- <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
- <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
- <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
- <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
<parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
<parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
<parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
- <parameter name="MEM_DDR3_TIS_PS" value="60" />
- <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
- <parameter name="MEM_DDR3_TIH_PS" value="95" />
- <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
- <parameter name="MEM_DDR3_TDS_PS" value="53" />
- <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
- <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="7" />
<parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
- <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
- <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
<parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
<parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
- <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
<parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
- <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
- <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
<parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
<parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
<parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
<parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
<parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
- <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
<parameter name="MEM_DDR3_TREFI_US" value="7.8" />
<parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
- <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
- <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
- <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
<parameter name="MEM_DDR3_TRRD_CYC" value="6" />
<parameter name="MEM_DDR3_TRTP_CYC" value="8" />
- <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
- <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
- <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
- <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
- <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
- <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
- <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
- <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
- <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
- <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="6" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
<parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
<parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
<parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
<parameter name="MEM_DDR4_DM_EN" value="true" />
- <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
- <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
- <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
- <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
- <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
- <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
- <parameter name="MEM_DDR4_RDIMM_CONFIG" value="0000000000000000" />
- <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
- <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
- <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
- <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
- <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
<parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
- <parameter name="MEM_DDR4_WRITE_CMD_LATENCY" value="4" />
- <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
- <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
- <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
- <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
<parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
- <parameter name="MEM_DDR4_CAL_MODE" value="0" />
- <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
- <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
- <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
- <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
- <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
- <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
- <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
- <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
- <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RDIMM_CONFIG" value="0000000000000000" />
<parameter name="MEM_DDR4_READ_DBI" value="false" />
- <parameter name="MEM_DDR4_VREFDQ_TRAINING_VALUE" value="60.0" />
- <parameter name="MEM_DDR4_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
- <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
- <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
- <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
- <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
- <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
<parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
- <parameter name="MEM_DDR4_WTCL" value="18" />
- <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
- <parameter name="MEM_DDR4_TCL" value="18" />
- <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
- <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
<parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
- <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
- <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
- <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
<parameter name="MEM_DDR4_R_ODT0_2X2" value="off,on" />
- <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
- <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
- <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
- <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
- <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
<parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
<parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
<parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
<parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
- <parameter name="MEM_DDR4_TIS_PS" value="60" />
- <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
- <parameter name="MEM_DDR4_TIH_PS" value="95" />
- <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="18" />
<parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
- <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
- <parameter name="MEM_DDR4_TDQSQ_PS" value="75" />
- <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="75" />
<parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
- <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
<parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
- <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
- <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="95" />
<parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="60" />
<parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
<parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
- <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
<parameter name="MEM_DDR4_TREFI_US" value="7.8" />
<parameter name="MEM_DDR4_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
<parameter name="MEM_DDR4_TWR_NS" value="15.0" />
<parameter name="MEM_DDR4_TWTR_L_CYC" value="4" />
<parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
- <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
- <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
- <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
- <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
- <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
- <parameter name="MEM_DDR4_TRTP_CYC" value="8" />
- <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="18" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
- <parameter name="MEM_QDR2_BWS_EN" value="true" />
<parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
<parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
<parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
<parameter name="MEM_QDR2_TSA_NS" value="0.23" />
- <parameter name="MEM_QDR2_THA_NS" value="0.18" />
<parameter name="MEM_QDR2_TSD_NS" value="0.23" />
- <parameter name="MEM_QDR2_THD_NS" value="0.18" />
- <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
- <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
- <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
- <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
- <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
- <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TAH_PS" value="125" />
+ <parameter name="MEM_QDR4_TAS_PS" value="125" />
+ <parameter name="MEM_QDR4_TCH_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCS_PS" value="150" />
+ <parameter name="MEM_QDR4_TIH_PS" value="125" />
+ <parameter name="MEM_QDR4_TIS_PS" value="125" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
<parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
<parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
- <parameter name="MEM_RLD2_DM_EN" value="true" />
<parameter name="MEM_RLD2_BL" value="4" />
<parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
<parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
<parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
- <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
<parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
- <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
- <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
- <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
<parameter name="MEM_RLD2_TAH_NS" value="0.3" />
- <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
- <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
- <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
- <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
<parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
<parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
<parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
- <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
<parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
<parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
- <parameter name="MEM_RLD3_DM_EN" value="true" />
<parameter name="MEM_RLD3_BL" value="2" />
<parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
- <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
- <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
<parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
- <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
- <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
<parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
- <parameter name="MEM_RLD3_TDS_PS" value="-30" />
- <parameter name="MEM_RLD3_TDH_PS" value="5" />
- <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
- <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
<parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
<parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
<parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
- <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
<parameter name="MEM_RLD3_TIH_PS" value="65" />
- <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
- <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
- <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
- <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
- <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
- <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
- <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
- <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
- <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
- <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
- <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
- <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
- <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
- <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
- <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
- <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
- <parameter name="CTRL_DDR3_ECC_EN" value="false" />
- <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
- <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
- <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
- <parameter name="CTRL_DDR3_MMR_EN" value="false" />
- <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
- <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
- <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
- <parameter name="CTRL_DDR4_ECC_EN" value="false" />
- <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
- <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
- <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
- <parameter name="CTRL_DDR4_MMR_EN" value="false" />
- <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
- <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
- <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
- <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
- <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
- <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
- <parameter name="DIAG_EXPORT_VJI" value="false" />
- <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
- <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
- <parameter name="DIAG_EXTRA_CONFIGS" value="" />
- <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
- <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
- <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
- <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
- <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
- <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
- <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
- <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index 50785cd112bb6506a053f9fb56069a1fcc26b89b..ec94bcebafe8bd2c40806cec8e86e452512e5e62 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -31,96 +31,96 @@ set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated_t
#vlib ./work/ ;# Assume library work already exists
-vmap ip_arria10_mac_10g_alt_em10g32_140 ./work/
+vmap ip_arria10_mac_10g_alt_em10g32_141 ./work/
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/alt_em10g32.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/alt_em10g32unit.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_creg_map.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_creg_top.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_top.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_preamble_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_top.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_ptp_request_controller.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/altera_avalon_dc_fifo.v" -work ip_arria10_mac_10g_alt_em10g32_140
-vlog "$IP_DIR/../alt_em10g32_140/sim/altera_dcfifo_synchronizer_bundle.v" -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/alt_em10g32.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/alt_em10g32unit.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_clk_rst.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_clock_crosser.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_crc32.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_creg_map.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_creg_top.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_frm_decoder.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_pipeline_base.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rst_cnt.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_frm_control.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_top.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_stat_mem.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_stat_reg.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_flow_control.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_pause_req.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_preamble_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_sc_fifo.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_top.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_altsyncram.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_gmii_tsu.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_lpm_mult.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_ptp_request_controller.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_crc328generator.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_crc32ctl8.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_crc32galois8.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/altera_avalon_dc_fifo.v" -work ip_arria10_mac_10g_alt_em10g32_141
+vlog "$IP_DIR/../alt_em10g32_141/sim/altera_dcfifo_synchronizer_bundle.v" -work ip_arria10_mac_10g_alt_em10g32_141
vcom "$IP_DIR/ip_arria10_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index bcd55797646df6bd5ec443f2f6a137cf71cad869..fc5620217242ecb6bd023bf2afff36a3fa8efe42 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_mac_10g
-hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_140
+hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_141
hdl_lib_uses =
hdl_lib_technology = ip_arria10
diff --git a/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
index 429b829758b8a3a358b011d8fa1a657b35951b33..bde01a26374abf3ebee18cbb52dd6d62b408966c 100644
--- a/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
+++ b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element alt_em10g32_0
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -40,69 +45,36 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
- <interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
- <port name="csr_read" internal="csr_read" />
- <port name="csr_write" internal="csr_write" />
- <port name="csr_writedata" internal="csr_writedata" />
- <port name="csr_readdata" internal="csr_readdata" />
- <port name="csr_waitrequest" internal="csr_waitrequest" />
- <port name="csr_address" internal="csr_address" />
- </interface>
- <interface
- name="tx_312_5_clk"
- internal="alt_em10g32_0.tx_312_5_clk"
- type="clock"
- dir="end">
- <port name="tx_312_5_clk" internal="tx_312_5_clk" />
- </interface>
- <interface
- name="tx_156_25_clk"
- internal="alt_em10g32_0.tx_156_25_clk"
- type="clock"
- dir="end">
- <port name="tx_156_25_clk" internal="tx_156_25_clk" />
- </interface>
- <interface
- name="rx_312_5_clk"
- internal="alt_em10g32_0.rx_312_5_clk"
- type="clock"
- dir="end">
- <port name="rx_312_5_clk" internal="rx_312_5_clk" />
- </interface>
- <interface
- name="rx_156_25_clk"
- internal="alt_em10g32_0.rx_156_25_clk"
- type="clock"
- dir="end">
- <port name="rx_156_25_clk" internal="rx_156_25_clk" />
- </interface>
- <interface
- name="csr_clk"
- internal="alt_em10g32_0.csr_clk"
- type="clock"
- dir="end">
- <port name="csr_clk" internal="csr_clk" />
- </interface>
<interface
- name="csr_rst_n"
- internal="alt_em10g32_0.csr_rst_n"
- type="reset"
+ name="avalon_st_pause"
+ internal="alt_em10g32_0.avalon_st_pause"
+ type="avalon_streaming"
dir="end">
- <port name="csr_rst_n" internal="csr_rst_n" />
+ <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
</interface>
<interface
- name="tx_rst_n"
- internal="alt_em10g32_0.tx_rst_n"
- type="reset"
- dir="end">
- <port name="tx_rst_n" internal="tx_rst_n" />
+ name="avalon_st_rx"
+ internal="alt_em10g32_0.avalon_st_rx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
+ <port
+ name="avalon_st_rx_startofpacket"
+ internal="avalon_st_rx_startofpacket" />
+ <port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
+ <port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
+ <port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
+ <port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
+ <port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
</interface>
<interface
- name="rx_rst_n"
- internal="alt_em10g32_0.rx_rst_n"
- type="reset"
- dir="end">
- <port name="rx_rst_n" internal="rx_rst_n" />
+ name="avalon_st_rxstatus"
+ internal="alt_em10g32_0.avalon_st_rxstatus"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
+ <port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
+ <port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
</interface>
<interface
name="avalon_st_tx"
@@ -119,20 +91,6 @@
<port name="avalon_st_tx_error" internal="avalon_st_tx_error" />
<port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" />
</interface>
- <interface
- name="avalon_st_pause"
- internal="alt_em10g32_0.avalon_st_pause"
- type="avalon_streaming"
- dir="end">
- <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
- </interface>
- <interface
- name="xgmii_tx"
- internal="alt_em10g32_0.xgmii_tx"
- type="avalon_streaming"
- dir="start">
- <port name="xgmii_tx" internal="xgmii_tx" />
- </interface>
<interface
name="avalon_st_txstatus"
internal="alt_em10g32_0.avalon_st_txstatus"
@@ -142,12 +100,27 @@
<port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" />
<port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" />
</interface>
+ <interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
+ <port name="csr_read" internal="csr_read" />
+ <port name="csr_write" internal="csr_write" />
+ <port name="csr_writedata" internal="csr_writedata" />
+ <port name="csr_readdata" internal="csr_readdata" />
+ <port name="csr_waitrequest" internal="csr_waitrequest" />
+ <port name="csr_address" internal="csr_address" />
+ </interface>
<interface
- name="xgmii_rx"
- internal="alt_em10g32_0.xgmii_rx"
- type="avalon_streaming"
+ name="csr_clk"
+ internal="alt_em10g32_0.csr_clk"
+ type="clock"
dir="end">
- <port name="xgmii_rx" internal="xgmii_rx" />
+ <port name="csr_clk" internal="csr_clk" />
+ </interface>
+ <interface
+ name="csr_rst_n"
+ internal="alt_em10g32_0.csr_rst_n"
+ type="reset"
+ dir="end">
+ <port name="csr_rst_n" internal="csr_rst_n" />
</interface>
<interface
name="link_fault_status_xgmii_rx"
@@ -159,28 +132,46 @@
internal="link_fault_status_xgmii_rx_data" />
</interface>
<interface
- name="avalon_st_rx"
- internal="alt_em10g32_0.avalon_st_rx"
- type="avalon_streaming"
- dir="start">
- <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
- <port
- name="avalon_st_rx_startofpacket"
- internal="avalon_st_rx_startofpacket" />
- <port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
- <port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
- <port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
- <port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
- <port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
+ name="rx_156_25_clk"
+ internal="alt_em10g32_0.rx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_156_25_clk" internal="rx_156_25_clk" />
</interface>
<interface
- name="avalon_st_rxstatus"
- internal="alt_em10g32_0.avalon_st_rxstatus"
- type="avalon_streaming"
- dir="start">
- <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
- <port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
- <port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
+ name="rx_312_5_clk"
+ internal="alt_em10g32_0.rx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_312_5_clk" internal="rx_312_5_clk" />
+ </interface>
+ <interface
+ name="rx_rst_n"
+ internal="alt_em10g32_0.rx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="rx_rst_n" internal="rx_rst_n" />
+ </interface>
+ <interface
+ name="tx_156_25_clk"
+ internal="alt_em10g32_0.tx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_156_25_clk" internal="tx_156_25_clk" />
+ </interface>
+ <interface
+ name="tx_312_5_clk"
+ internal="alt_em10g32_0.tx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_312_5_clk" internal="tx_312_5_clk" />
+ </interface>
+ <interface
+ name="tx_rst_n"
+ internal="alt_em10g32_0.tx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="tx_rst_n" internal="tx_rst_n" />
</interface>
<interface
name="unidirectional"
@@ -192,35 +183,51 @@
name="unidirectional_remote_fault_dis"
internal="unidirectional_remote_fault_dis" />
</interface>
- <interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" />
- <interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" />
- <interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" />
+ <interface
+ name="xgmii_rx"
+ internal="alt_em10g32_0.xgmii_rx"
+ type="avalon_streaming"
+ dir="end">
+ <port name="xgmii_rx" internal="xgmii_rx" />
+ </interface>
<interface name="xgmii_rx_control" internal="alt_em10g32_0.xgmii_rx_control" />
+ <interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" />
+ <interface
+ name="xgmii_tx"
+ internal="alt_em10g32_0.xgmii_tx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="xgmii_tx" internal="xgmii_tx" />
+ </interface>
+ <interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" />
+ <interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" />
<module
+ name="alt_em10g32_0"
kind="alt_em10g32"
- version="14.0"
+ version="14.1"
enabled="1"
- name="alt_em10g32_0"
autoexport="1">
+ <parameter name="DATAPATH_OPTION" value="3" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
- <parameter name="INSERT_ST_ADAPTOR" value="1" />
+ <parameter name="ENABLE_10GBASER_REG_MODE" value="0" />
+ <parameter name="ENABLE_1G10G_MAC" value="0" />
+ <parameter name="ENABLE_MEM_ECC" value="0" />
+ <parameter name="ENABLE_PFC" value="0" />
+ <parameter name="ENABLE_PTP_1STEP" value="0" />
+ <parameter name="ENABLE_SUPP_ADDR" value="0" />
+ <parameter name="ENABLE_TIMESTAMPING" value="0" />
+ <parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
<parameter name="INSERT_CSR_ADAPTOR" value="1" />
+ <parameter name="INSERT_ST_ADAPTOR" value="1" />
<parameter name="INSERT_XGMII_ADAPTOR" value="1" />
- <parameter name="DATAPATH_OPTION" value="3" />
- <parameter name="ENABLE_SUPP_ADDR" value="0" />
- <parameter name="ENABLE_PFC" value="0" />
- <parameter name="PFC_PRIORITY_NUMBER" value="8" />
<parameter name="INSTANTIATE_STATISTICS" value="0" />
- <parameter name="REGISTER_BASED_STATISTICS" value="0" />
+ <parameter name="PFC_PRIORITY_NUMBER" value="8" />
<parameter name="PREAMBLE_PASSTHROUGH" value="0" />
- <parameter name="ENABLE_TIMESTAMPING" value="0" />
- <parameter name="ENABLE_PTP_1STEP" value="0" />
+ <parameter name="REGISTER_BASED_STATISTICS" value="0" />
+ <parameter name="TIME_OF_DAY_FORMAT" value="2" />
<parameter name="TSTAMP_FP_WIDTH" value="4" />
- <parameter name="ENABLE_1G10G_MAC" value="0" />
- <parameter name="ENABLE_MEM_ECC" value="0" />
- <parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index eafcc4e48d906f7094ad13efbb48f50b3bb0f0a5..29305b65ab51cb2073d5197af5220847bb3756f7 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -30,82 +30,82 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/phy_10gbase_r/gener
#vlib ./work/ ;# Assume library work already exists
-vmap ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140 ./work/
+vmap ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141 ./work/
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/altera_xcvr_functions.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pcs.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pcs_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pma.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_pma_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_xcvr_native.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pcs.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pcs_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pma.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_pma_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_xcvr_native.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/altera_xcvr_native_a10.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/altera_xcvr_native_a10.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_native_a10_140/sim/mentor/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/altera_xcvr_functions.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/alt_xcvr_resync.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_pcs.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_pcs_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_pma.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_pma_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_xcvr_native.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_pcs.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_pcs_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_pma.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_pma_ch.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_xcvr_native.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_10g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_10g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_8g_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_8g_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_common_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_common_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_fifo_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_fifo_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_gen3_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_gen3_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_krfec_rx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_krfec_tx_pcs_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pipe_gen1_2_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pipe_gen3_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_rx_dfe_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_rx_odi_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_rx_sd_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_tx_buf_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_tx_cgb_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_pma_tx_ser_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_rx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_rx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_tx_pcs_pma_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/twentynm_hssi_tx_pld_pcs_interface_rbc.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/a10_avmm_h.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/altera_xcvr_native_a10.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/a10_avmm_h.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/altera_xcvr_native_a10.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/alt_xcvr_native_avmm_csr.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/alt_xcvr_native_prbs_accum.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_native_a10_141/sim/mentor/alt_xcvr_native_embedded_debug.sv" -work ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
vcom "$IP_DIR/ip_arria10_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index 749313a883e0354111dc61468cc9a98293dfd3e8..33e4b6072b76d2893ecc37e49844c27d676e603c 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_140
+hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_141
hdl_lib_uses =
hdl_lib_technology = ip_arria10
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
index f3dab4dd161cd4004b2bb15d60971204318e7261..c9ce27ba7dee0398d38c69e2d749d4c2623660be 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element xcvr_native_a10_0
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -41,123 +46,116 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="tx_analogreset"
- internal="xcvr_native_a10_0.tx_analogreset"
- type="conduit"
- dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
- name="tx_digitalreset"
- internal="xcvr_native_a10_0.tx_digitalreset"
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="rx_analogreset"
- internal="xcvr_native_a10_0.rx_analogreset"
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="rx_digitalreset"
- internal="xcvr_native_a10_0.rx_digitalreset"
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
</interface>
<interface
- name="tx_cal_busy"
- internal="xcvr_native_a10_0.tx_cal_busy"
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_clkout" internal="rx_clkout" />
</interface>
<interface
- name="rx_cal_busy"
- internal="xcvr_native_a10_0.rx_cal_busy"
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="rx_control" internal="rx_control" />
</interface>
<interface
- name="tx_serial_clk0"
- internal="xcvr_native_a10_0.tx_serial_clk0"
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
</interface>
<interface
- name="rx_cdr_refclk0"
- internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_serial_data"
- internal="xcvr_native_a10_0.tx_serial_data"
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
type="conduit"
dir="end">
- <port name="tx_serial_data" internal="tx_serial_data" />
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
</interface>
<interface
- name="rx_serial_data"
- internal="xcvr_native_a10_0.rx_serial_data"
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
type="conduit"
dir="end">
- <port name="rx_serial_data" internal="rx_serial_data" />
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
</interface>
<interface
- name="rx_is_lockedtoref"
- internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
type="conduit"
dir="end">
- <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
</interface>
<interface
- name="tx_coreclkin"
- internal="xcvr_native_a10_0.tx_coreclkin"
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
type="conduit"
dir="end">
- <port name="tx_coreclkin" internal="tx_coreclkin" />
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
</interface>
<interface
- name="rx_coreclkin"
- internal="xcvr_native_a10_0.rx_coreclkin"
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
type="conduit"
dir="end">
- <port name="rx_coreclkin" internal="rx_coreclkin" />
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
</interface>
<interface
- name="tx_clkout"
- internal="xcvr_native_a10_0.tx_clkout"
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
type="conduit"
dir="end">
- <port name="tx_clkout" internal="tx_clkout" />
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
</interface>
<interface
- name="rx_clkout"
- internal="xcvr_native_a10_0.rx_clkout"
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="rx_clkout" internal="rx_clkout" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="tx_parallel_data"
- internal="xcvr_native_a10_0.tx_parallel_data"
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
type="conduit"
dir="end">
- <port name="tx_parallel_data" internal="tx_parallel_data" />
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
</interface>
<interface
name="rx_parallel_data"
@@ -167,67 +165,67 @@
<port name="rx_parallel_data" internal="rx_parallel_data" />
</interface>
<interface
- name="tx_pma_div_clkout"
- internal="xcvr_native_a10_0.tx_pma_div_clkout"
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
type="conduit"
dir="end">
- <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
+ <port name="rx_serial_data" internal="rx_serial_data" />
</interface>
<interface
- name="tx_control"
- internal="xcvr_native_a10_0.tx_control"
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
type="conduit"
dir="end">
- <port name="tx_control" internal="tx_control" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="tx_err_ins"
- internal="xcvr_native_a10_0.tx_err_ins"
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
type="conduit"
dir="end">
- <port name="tx_err_ins" internal="tx_err_ins" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="unused_tx_parallel_data"
- internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
type="conduit"
dir="end">
- <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ <port name="tx_clkout" internal="tx_clkout" />
</interface>
<interface
- name="unused_tx_control"
- internal="xcvr_native_a10_0.unused_tx_control"
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
type="conduit"
dir="end">
- <port name="unused_tx_control" internal="unused_tx_control" />
+ <port name="tx_control" internal="tx_control" />
</interface>
<interface
- name="rx_control"
- internal="xcvr_native_a10_0.rx_control"
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
type="conduit"
dir="end">
- <port name="rx_control" internal="rx_control" />
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
</interface>
<interface
- name="unused_rx_parallel_data"
- internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
type="conduit"
dir="end">
- <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="unused_rx_control"
- internal="xcvr_native_a10_0.unused_rx_control"
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
type="conduit"
dir="end">
- <port name="unused_rx_control" internal="unused_rx_control" />
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
</interface>
<interface
- name="tx_enh_data_valid"
- internal="xcvr_native_a10_0.tx_enh_data_valid"
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
type="conduit"
dir="end">
- <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
</interface>
<interface
name="tx_enh_fifo_full"
@@ -236,6 +234,13 @@
dir="end">
<port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
</interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
<interface
name="tx_enh_fifo_pfull"
internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
@@ -244,269 +249,223 @@
<port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
</interface>
<interface
- name="tx_enh_fifo_empty"
- internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
type="conduit"
dir="end">
- <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ <port name="tx_err_ins" internal="tx_err_ins" />
</interface>
<interface
- name="tx_enh_fifo_pempty"
- internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
</interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
<interface
- name="rx_enh_data_valid"
- internal="xcvr_native_a10_0.rx_enh_data_valid"
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout"
type="conduit"
dir="end">
- <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
</interface>
<interface
- name="rx_enh_fifo_full"
- internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
type="conduit"
dir="end">
- <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
</interface>
<interface
- name="rx_enh_fifo_empty"
- internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
type="conduit"
dir="end">
- <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ <port name="tx_serial_data" internal="tx_serial_data" />
</interface>
<interface
- name="rx_enh_fifo_del"
- internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
type="conduit"
dir="end">
- <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ <port name="unused_rx_control" internal="unused_rx_control" />
</interface>
<interface
- name="rx_enh_fifo_insert"
- internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
</interface>
<interface
- name="rx_enh_highber"
- internal="xcvr_native_a10_0.rx_enh_highber"
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
type="conduit"
dir="end">
- <port name="rx_enh_highber" internal="rx_enh_highber" />
+ <port name="unused_tx_control" internal="unused_tx_control" />
</interface>
<interface
- name="rx_enh_blk_lock"
- internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
</interface>
- <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
<module
+ name="xcvr_native_a10_0"
kind="altera_xcvr_native_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="xcvr_native_a10_0"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="Unknown" />
- <parameter name="design_environment" value="NATIVE" />
- <parameter name="message_level" value="error" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="protocol_mode" value="teng_baser_mode" />
- <parameter name="pma_mode" value="basic" />
- <parameter name="duplex_mode" value="duplex" />
- <parameter name="channels" value="1" />
- <parameter name="set_data_rate" value="10312.5" />
- <parameter name="rcfg_iface_enable" value="0" />
- <parameter name="enable_simple_interface" value="1" />
- <parameter name="enable_split_interface" value="0" />
- <parameter name="set_enable_calibration" value="0" />
- <parameter name="enable_transparent_pcs" value="0" />
- <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
- <parameter name="set_pcs_bonding_master" value="Auto" />
- <parameter name="tx_pma_clk_div" value="1" />
- <parameter name="plls" value="1" />
- <parameter name="pll_select" value="0" />
- <parameter name="enable_port_tx_pma_clkout" value="0" />
- <parameter name="enable_port_tx_pma_div_clkout" value="1" />
- <parameter name="tx_pma_div_clkout_divider" value="33" />
- <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_tx_pma_elecidle" value="0" />
- <parameter name="enable_port_tx_pma_qpipullup" value="0" />
- <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
- <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
- <parameter name="enable_port_tx_pma_rxfound" value="0" />
- <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
- <parameter name="set_cdr_refclk_freq" value="644.531250" />
- <parameter name="rx_ppm_detect_threshold" value="1000" />
- <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
- <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
- <parameter name="rx_pma_dfe_fixed_taps" value="3" />
- <parameter name="enable_rx_pma_floatingtap" value="0" />
- <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="channels" value="1" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
<parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
- <parameter name="rx_pma_div_clkout_divider" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
- <parameter name="enable_port_rx_is_lockedtodata" value="1" />
- <parameter name="enable_port_rx_is_lockedtoref" value="1" />
- <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
- <parameter name="enable_ports_rx_manual_ppm" value="0" />
- <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
- <parameter name="enable_ports_rx_prbs" value="0" />
- <parameter name="std_pcs_pma_width" value="10" />
- <parameter name="std_low_latency_bypass_enable" value="0" />
- <parameter name="enable_hip" value="0" />
- <parameter name="enable_hard_reset" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
- <parameter name="std_tx_pcfifo_mode" value="low_latency" />
- <parameter name="std_rx_pcfifo_mode" value="low_latency" />
- <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
<parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
- <parameter name="std_tx_byte_ser_mode" value="Disabled" />
- <parameter name="std_rx_byte_deser_mode" value="Disabled" />
- <parameter name="std_tx_8b10b_enable" value="0" />
- <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
- <parameter name="std_rx_8b10b_enable" value="0" />
- <parameter name="std_rx_rmfifo_mode" value="disabled" />
- <parameter name="std_rx_rmfifo_pattern_n" value="0" />
- <parameter name="std_rx_rmfifo_pattern_p" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
<parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
- <parameter name="pcie_rate_match" value="Bypass" />
- <parameter name="std_tx_bitslip_enable" value="0" />
- <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
- <parameter name="std_rx_word_aligner_mode" value="bitslip" />
- <parameter name="std_rx_word_aligner_pattern_len" value="7" />
- <parameter name="std_rx_word_aligner_pattern" value="0" />
- <parameter name="std_rx_word_aligner_rknumber" value="3" />
- <parameter name="std_rx_word_aligner_renumber" value="3" />
- <parameter name="std_rx_word_aligner_rgnumber" value="3" />
- <parameter name="std_rx_word_aligner_rvnumber" value="0" />
- <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
- <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
<parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
- <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
- <parameter name="enable_port_rx_std_bitslip" value="0" />
- <parameter name="std_tx_bitrev_enable" value="0" />
- <parameter name="std_tx_byterev_enable" value="0" />
- <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
<parameter name="enable_port_tx_polinv" value="0" />
- <parameter name="std_rx_bitrev_enable" value="0" />
- <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
- <parameter name="std_rx_byterev_enable" value="0" />
- <parameter name="enable_port_rx_std_byterev_ena" value="0" />
- <parameter name="std_rx_polinv_enable" value="0" />
- <parameter name="enable_port_rx_polinv" value="0" />
- <parameter name="enable_port_rx_std_signaldetect" value="0" />
- <parameter name="enable_ports_pipe_sw" value="0" />
- <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
<parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
<parameter name="enable_ports_pipe_rx_elecidle" value="0" />
- <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="0" />
+ <parameter name="enable_rx_pma_floatingtap" value="0" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
<parameter name="enh_pcs_pma_width" value="32" />
<parameter name="enh_pld_pcs_width" value="66" />
- <parameter name="enh_low_latency_enable" value="0" />
- <parameter name="enh_rxtxfifo_double_width" value="0" />
- <parameter name="enh_txfifo_mode" value="Phase compensation" />
- <parameter name="enh_txfifo_pfull" value="11" />
- <parameter name="enh_txfifo_pempty" value="2" />
- <parameter name="enable_port_tx_enh_fifo_full" value="1" />
- <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
- <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
- <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
- <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
- <parameter name="enh_rxfifo_mode" value="10GBase-R" />
- <parameter name="enh_rxfifo_pfull" value="23" />
- <parameter name="enh_rxfifo_pempty" value="2" />
- <parameter name="enh_rxfifo_align_del" value="0" />
- <parameter name="enh_rxfifo_control_del" value="0" />
- <parameter name="enable_port_rx_enh_data_valid" value="1" />
- <parameter name="enable_port_rx_enh_fifo_full" value="1" />
- <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
- <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
- <parameter name="enable_port_rx_enh_fifo_del" value="1" />
- <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
- <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
- <parameter name="enh_tx_frmgen_enable" value="0" />
- <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
- <parameter name="enh_tx_frmgen_burst_enable" value="0" />
- <parameter name="enable_port_tx_enh_frame" value="0" />
- <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
- <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
- <parameter name="enh_rx_frmsync_enable" value="0" />
- <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
- <parameter name="enable_port_rx_enh_frame" value="0" />
- <parameter name="enable_port_rx_enh_frame_lock" value="0" />
- <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
- <parameter name="enh_tx_crcgen_enable" value="0" />
- <parameter name="enh_tx_crcerr_enable" value="0" />
- <parameter name="enh_rx_crcchk_enable" value="0" />
- <parameter name="enable_port_rx_enh_crc32_err" value="0" />
- <parameter name="enable_port_rx_enh_highber" value="1" />
- <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
- <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
- <parameter name="enh_tx_64b66b_enable" value="1" />
<parameter name="enh_rx_64b66b_enable" value="1" />
- <parameter name="enh_tx_sh_err" value="0" />
- <parameter name="enh_tx_scram_enable" value="1" />
- <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
<parameter name="enh_rx_descram_enable" value="1" />
- <parameter name="enh_tx_dispgen_enable" value="0" />
<parameter name="enh_rx_dispchk_enable" value="0" />
- <parameter name="enh_rx_blksync_enable" value="1" />
- <parameter name="enable_port_rx_enh_blk_lock" value="1" />
- <parameter name="enh_tx_bitslip_enable" value="0" />
- <parameter name="enh_tx_polinv_enable" value="0" />
- <parameter name="enh_rx_bitslip_enable" value="0" />
- <parameter name="enh_rx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_enh_bitslip" value="0" />
- <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enh_rx_krfec_err_mark_enable" value="0" />
<parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
<parameter name="enh_tx_krfec_burst_err_enable" value="0" />
<parameter name="enh_tx_krfec_burst_err_len" value="1" />
- <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
- <parameter name="pcs_direct_width" value="8" />
- <parameter name="generate_docs" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
<parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="validation_rule_select" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rapid_validate" value="0" />
<parameter name="rcfg_enable" value="0" />
- <parameter name="rcfg_shared" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
- <parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
@@ -515,8 +474,58 @@
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys b/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
index ccd801725a10ef56181afb8de27b155e94494d66..bfe10860d718e978dfe71d958014942f54a5f934 100644
--- a/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_phy_inst
{
@@ -23,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115R2F40I2LG" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@@ -41,74 +46,67 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="tx_analogreset"
- internal="transceiver_phy_inst.tx_analogreset"
- type="conduit"
- dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
- name="tx_digitalreset"
- internal="transceiver_phy_inst.tx_digitalreset"
+ name="rx_analogreset"
+ internal="transceiver_phy_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_phy_inst.rx_analogreset"
+ name="rx_cal_busy"
+ internal="transceiver_phy_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_phy_inst.rx_digitalreset"
+ name="rx_cdr_refclk0"
+ internal="transceiver_phy_inst.rx_cdr_refclk0"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_phy_inst.tx_cal_busy"
+ name="rx_clkout"
+ internal="transceiver_phy_inst.rx_clkout"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_clkout" internal="rx_clkout" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_phy_inst.rx_cal_busy"
+ name="rx_control"
+ internal="transceiver_phy_inst.rx_control"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="rx_control" internal="rx_control" />
</interface>
<interface
- name="tx_serial_clk0"
- internal="transceiver_phy_inst.tx_serial_clk0"
+ name="rx_coreclkin"
+ internal="transceiver_phy_inst.rx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
</interface>
<interface
- name="rx_cdr_refclk0"
- internal="transceiver_phy_inst.rx_cdr_refclk0"
+ name="rx_digitalreset"
+ internal="transceiver_phy_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_serial_data"
- internal="transceiver_phy_inst.tx_serial_data"
+ name="rx_enh_blk_lock"
+ internal="transceiver_phy_inst.rx_enh_blk_lock"
type="conduit"
dir="end">
- <port name="tx_serial_data" internal="tx_serial_data" />
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
</interface>
<interface
- name="rx_serial_data"
- internal="transceiver_phy_inst.rx_serial_data"
+ name="rx_enh_data_valid"
+ internal="transceiver_phy_inst.rx_enh_data_valid"
type="conduit"
dir="end">
- <port name="rx_serial_data" internal="rx_serial_data" />
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
</interface>
<interface
name="rx_is_lockedtodata"
@@ -118,39 +116,43 @@
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="tx_coreclkin"
- internal="transceiver_phy_inst.tx_coreclkin"
+ name="rx_parallel_data"
+ internal="transceiver_phy_inst.rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_coreclkin" internal="tx_coreclkin" />
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
</interface>
+ <interface name="rx_pma_clkout" internal="transceiver_phy_inst.rx_pma_clkout" />
<interface
- name="rx_coreclkin"
- internal="transceiver_phy_inst.rx_coreclkin"
+ name="rx_pma_div_clkout"
+ internal="transceiver_phy_inst.rx_pma_div_clkout" />
+ <interface
+ name="rx_serial_data"
+ internal="transceiver_phy_inst.rx_serial_data"
type="conduit"
dir="end">
- <port name="rx_coreclkin" internal="rx_coreclkin" />
+ <port name="rx_serial_data" internal="rx_serial_data" />
</interface>
<interface
- name="tx_clkout"
- internal="transceiver_phy_inst.tx_clkout"
+ name="tx_analogreset"
+ internal="transceiver_phy_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="tx_clkout" internal="tx_clkout" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_clkout"
- internal="transceiver_phy_inst.rx_clkout"
+ name="tx_cal_busy"
+ internal="transceiver_phy_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_clkout" internal="rx_clkout" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="tx_parallel_data"
- internal="transceiver_phy_inst.tx_parallel_data"
+ name="tx_clkout"
+ internal="transceiver_phy_inst.tx_clkout"
type="conduit"
dir="end">
- <port name="tx_parallel_data" internal="tx_parallel_data" />
+ <port name="tx_clkout" internal="tx_clkout" />
</interface>
<interface
name="tx_control"
@@ -160,293 +162,250 @@
<port name="tx_control" internal="tx_control" />
</interface>
<interface
- name="tx_err_ins"
- internal="transceiver_phy_inst.tx_err_ins"
+ name="tx_coreclkin"
+ internal="transceiver_phy_inst.tx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_err_ins" internal="tx_err_ins" />
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
</interface>
<interface
- name="unused_tx_parallel_data"
- internal="transceiver_phy_inst.unused_tx_parallel_data"
+ name="tx_digitalreset"
+ internal="transceiver_phy_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="unused_tx_control"
- internal="transceiver_phy_inst.unused_tx_control"
+ name="tx_enh_data_valid"
+ internal="transceiver_phy_inst.tx_enh_data_valid"
type="conduit"
dir="end">
- <port name="unused_tx_control" internal="unused_tx_control" />
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
</interface>
<interface
- name="rx_parallel_data"
- internal="transceiver_phy_inst.rx_parallel_data"
+ name="tx_err_ins"
+ internal="transceiver_phy_inst.tx_err_ins"
type="conduit"
dir="end">
- <port name="rx_parallel_data" internal="rx_parallel_data" />
+ <port name="tx_err_ins" internal="tx_err_ins" />
</interface>
<interface
- name="rx_control"
- internal="transceiver_phy_inst.rx_control"
+ name="tx_parallel_data"
+ internal="transceiver_phy_inst.tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_control" internal="rx_control" />
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
</interface>
<interface
- name="unused_rx_parallel_data"
- internal="transceiver_phy_inst.unused_rx_parallel_data"
+ name="tx_pma_clkout"
+ internal="transceiver_phy_inst.tx_pma_clkout"
type="conduit"
dir="end">
- <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ <port name="tx_pma_clkout" internal="tx_pma_clkout" />
</interface>
<interface
- name="unused_rx_control"
- internal="transceiver_phy_inst.unused_rx_control"
+ name="tx_pma_div_clkout"
+ internal="transceiver_phy_inst.tx_pma_div_clkout"
type="conduit"
dir="end">
- <port name="unused_rx_control" internal="unused_rx_control" />
+ <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
</interface>
<interface
- name="tx_enh_data_valid"
- internal="transceiver_phy_inst.tx_enh_data_valid"
+ name="tx_serial_clk0"
+ internal="transceiver_phy_inst.tx_serial_clk0"
type="conduit"
dir="end">
- <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
</interface>
<interface
- name="rx_enh_data_valid"
- internal="transceiver_phy_inst.rx_enh_data_valid"
+ name="tx_serial_data"
+ internal="transceiver_phy_inst.tx_serial_data"
type="conduit"
dir="end">
- <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ <port name="tx_serial_data" internal="tx_serial_data" />
</interface>
<interface
- name="rx_enh_blk_lock"
- internal="transceiver_phy_inst.rx_enh_blk_lock"
+ name="unused_rx_control"
+ internal="transceiver_phy_inst.unused_rx_control"
type="conduit"
dir="end">
- <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ <port name="unused_rx_control" internal="unused_rx_control" />
</interface>
<interface
- name="tx_pma_div_clkout"
- internal="transceiver_phy_inst.tx_pma_div_clkout"
+ name="unused_rx_parallel_data"
+ internal="transceiver_phy_inst.unused_rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
</interface>
<interface
- name="tx_pma_clkout"
- internal="transceiver_phy_inst.tx_pma_clkout"
+ name="unused_tx_control"
+ internal="transceiver_phy_inst.unused_tx_control"
type="conduit"
dir="end">
- <port name="tx_pma_clkout" internal="tx_pma_clkout" />
+ <port name="unused_tx_control" internal="unused_tx_control" />
</interface>
- <interface name="rx_pma_clkout" internal="transceiver_phy_inst.rx_pma_clkout" />
<interface
- name="rx_pma_div_clkout"
- internal="transceiver_phy_inst.rx_pma_div_clkout" />
+ name="unused_tx_parallel_data"
+ internal="transceiver_phy_inst.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
<module
+ name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_phy_inst"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115R2F40I2LG" />
- <parameter name="design_environment" value="NATIVE" />
- <parameter name="message_level" value="error" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="protocol_mode" value="teng_baser_mode" />
- <parameter name="pma_mode" value="basic" />
- <parameter name="duplex_mode" value="duplex" />
- <parameter name="channels" value="1" />
- <parameter name="set_data_rate" value="10312.5" />
- <parameter name="rcfg_iface_enable" value="0" />
- <parameter name="enable_simple_interface" value="1" />
- <parameter name="enable_split_interface" value="0" />
- <parameter name="set_enable_calibration" value="0" />
- <parameter name="enable_transparent_pcs" value="0" />
- <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
- <parameter name="set_pcs_bonding_master" value="Auto" />
- <parameter name="tx_pma_clk_div" value="1" />
- <parameter name="plls" value="1" />
- <parameter name="pll_select" value="0" />
- <parameter name="enable_port_tx_pma_clkout" value="1" />
- <parameter name="enable_port_tx_pma_div_clkout" value="1" />
- <parameter name="tx_pma_div_clkout_divider" value="33" />
- <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_tx_pma_elecidle" value="0" />
- <parameter name="enable_port_tx_pma_qpipullup" value="0" />
- <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
- <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
- <parameter name="enable_port_tx_pma_rxfound" value="0" />
- <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
- <parameter name="set_cdr_refclk_freq" value="644.531250" />
- <parameter name="rx_ppm_detect_threshold" value="100" />
- <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
- <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
- <parameter name="rx_pma_dfe_fixed_taps" value="3" />
- <parameter name="enable_rx_pma_floatingtap" value="0" />
- <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="channels" value="1" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="0" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="0" />
<parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
- <parameter name="rx_pma_div_clkout_divider" value="66" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
- <parameter name="enable_port_rx_is_lockedtodata" value="1" />
- <parameter name="enable_port_rx_is_lockedtoref" value="0" />
- <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
- <parameter name="enable_ports_rx_manual_ppm" value="0" />
- <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
- <parameter name="enable_ports_rx_prbs" value="0" />
- <parameter name="std_pcs_pma_width" value="10" />
- <parameter name="std_low_latency_bypass_enable" value="0" />
- <parameter name="enable_hip" value="0" />
- <parameter name="enable_hard_reset" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
- <parameter name="std_tx_pcfifo_mode" value="low_latency" />
- <parameter name="std_rx_pcfifo_mode" value="low_latency" />
- <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
<parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
- <parameter name="std_tx_byte_ser_mode" value="Disabled" />
- <parameter name="std_rx_byte_deser_mode" value="Disabled" />
- <parameter name="std_tx_8b10b_enable" value="1" />
- <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
- <parameter name="std_rx_8b10b_enable" value="1" />
- <parameter name="std_rx_rmfifo_mode" value="disabled" />
- <parameter name="std_rx_rmfifo_pattern_n" value="0" />
- <parameter name="std_rx_rmfifo_pattern_p" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
<parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
- <parameter name="pcie_rate_match" value="Bypass" />
- <parameter name="std_tx_bitslip_enable" value="0" />
- <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
- <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
- <parameter name="std_rx_word_aligner_pattern_len" value="7" />
- <parameter name="std_rx_word_aligner_pattern" value="124" />
- <parameter name="std_rx_word_aligner_rknumber" value="3" />
- <parameter name="std_rx_word_aligner_renumber" value="3" />
- <parameter name="std_rx_word_aligner_rgnumber" value="3" />
- <parameter name="std_rx_word_aligner_rvnumber" value="0" />
- <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
- <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
<parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
- <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
- <parameter name="enable_port_rx_std_bitslip" value="0" />
- <parameter name="std_tx_bitrev_enable" value="0" />
- <parameter name="std_tx_byterev_enable" value="0" />
- <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="1" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
<parameter name="enable_port_tx_polinv" value="0" />
- <parameter name="std_rx_bitrev_enable" value="0" />
- <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
- <parameter name="std_rx_byterev_enable" value="0" />
- <parameter name="enable_port_rx_std_byterev_ena" value="0" />
- <parameter name="std_rx_polinv_enable" value="0" />
- <parameter name="enable_port_rx_polinv" value="0" />
- <parameter name="enable_port_rx_std_signaldetect" value="0" />
- <parameter name="enable_ports_pipe_sw" value="0" />
- <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
<parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
<parameter name="enable_ports_pipe_rx_elecidle" value="0" />
- <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="0" />
+ <parameter name="enable_rx_pma_floatingtap" value="0" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
<parameter name="enh_pcs_pma_width" value="32" />
<parameter name="enh_pld_pcs_width" value="66" />
- <parameter name="enh_low_latency_enable" value="0" />
- <parameter name="enh_rxtxfifo_double_width" value="0" />
- <parameter name="enh_txfifo_mode" value="Phase compensation" />
- <parameter name="enh_txfifo_pfull" value="11" />
- <parameter name="enh_txfifo_pempty" value="2" />
- <parameter name="enable_port_tx_enh_fifo_full" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
- <parameter name="enh_rxfifo_mode" value="10GBase-R" />
- <parameter name="enh_rxfifo_pfull" value="23" />
- <parameter name="enh_rxfifo_pempty" value="2" />
- <parameter name="enh_rxfifo_align_del" value="0" />
- <parameter name="enh_rxfifo_control_del" value="0" />
- <parameter name="enable_port_rx_enh_data_valid" value="1" />
- <parameter name="enable_port_rx_enh_fifo_full" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
- <parameter name="enable_port_rx_enh_fifo_del" value="0" />
- <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
- <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
- <parameter name="enh_tx_frmgen_enable" value="0" />
- <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
- <parameter name="enh_tx_frmgen_burst_enable" value="0" />
- <parameter name="enable_port_tx_enh_frame" value="0" />
- <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
- <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
- <parameter name="enh_rx_frmsync_enable" value="0" />
- <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
- <parameter name="enable_port_rx_enh_frame" value="0" />
- <parameter name="enable_port_rx_enh_frame_lock" value="0" />
- <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
- <parameter name="enh_tx_crcgen_enable" value="0" />
- <parameter name="enh_tx_crcerr_enable" value="0" />
- <parameter name="enh_rx_crcchk_enable" value="0" />
- <parameter name="enable_port_rx_enh_crc32_err" value="0" />
- <parameter name="enable_port_rx_enh_highber" value="0" />
- <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
- <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
- <parameter name="enh_tx_64b66b_enable" value="1" />
<parameter name="enh_rx_64b66b_enable" value="1" />
- <parameter name="enh_tx_sh_err" value="0" />
- <parameter name="enh_tx_scram_enable" value="1" />
- <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
<parameter name="enh_rx_descram_enable" value="1" />
- <parameter name="enh_tx_dispgen_enable" value="0" />
<parameter name="enh_rx_dispchk_enable" value="0" />
- <parameter name="enh_rx_blksync_enable" value="1" />
- <parameter name="enable_port_rx_enh_blk_lock" value="1" />
- <parameter name="enh_tx_bitslip_enable" value="0" />
- <parameter name="enh_tx_polinv_enable" value="0" />
- <parameter name="enh_rx_bitslip_enable" value="0" />
- <parameter name="enh_rx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_enh_bitslip" value="0" />
- <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enh_rx_krfec_err_mark_enable" value="0" />
<parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
<parameter name="enh_tx_krfec_burst_err_enable" value="0" />
<parameter name="enh_tx_krfec_burst_err_len" value="1" />
- <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
- <parameter name="pcs_direct_width" value="8" />
- <parameter name="generate_docs" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
<parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="validation_rule_select" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rapid_validate" value="0" />
<parameter name="rcfg_enable" value="0" />
- <parameter name="rcfg_shared" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
- <parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
@@ -455,8 +414,58 @@
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="66" />
+ <parameter name="rx_ppm_detect_threshold" value="100" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="1" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
+ <parameter name="std_rx_word_aligner_pattern" value="124" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="1" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys b/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
index 30aa564f44631bc6855a2cad9c52d60889d2f40c..315a907a703f96a5d5feb2e2f1a05274657e37fb 100644
--- a/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_phy_inst
{
@@ -41,422 +46,376 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="tx_analogreset"
- internal="transceiver_phy_inst.tx_analogreset"
+ name="rx_analogreset"
+ internal="transceiver_phy_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_phy_inst.tx_digitalreset"
+ name="rx_cal_busy"
+ internal="transceiver_phy_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_phy_inst.rx_analogreset"
+ name="rx_cdr_refclk0"
+ internal="transceiver_phy_inst.rx_cdr_refclk0"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_phy_inst.rx_digitalreset"
+ name="rx_clkout"
+ internal="transceiver_phy_inst.rx_clkout"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="rx_clkout" internal="rx_clkout" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_phy_inst.tx_cal_busy"
+ name="rx_control"
+ internal="transceiver_phy_inst.rx_control"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_control" internal="rx_control" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_phy_inst.rx_cal_busy"
+ name="rx_coreclkin"
+ internal="transceiver_phy_inst.rx_coreclkin"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
</interface>
<interface
- name="tx_serial_clk0"
- internal="transceiver_phy_inst.tx_serial_clk0"
+ name="rx_digitalreset"
+ internal="transceiver_phy_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="rx_cdr_refclk0"
- internal="transceiver_phy_inst.rx_cdr_refclk0"
+ name="rx_enh_blk_lock"
+ internal="transceiver_phy_inst.rx_enh_blk_lock"
type="conduit"
dir="end">
- <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
</interface>
<interface
- name="tx_serial_data"
- internal="transceiver_phy_inst.tx_serial_data"
+ name="rx_enh_data_valid"
+ internal="transceiver_phy_inst.rx_enh_data_valid"
type="conduit"
dir="end">
- <port name="tx_serial_data" internal="tx_serial_data" />
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
</interface>
<interface
- name="rx_serial_data"
- internal="transceiver_phy_inst.rx_serial_data"
+ name="rx_is_lockedtodata"
+ internal="transceiver_phy_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="rx_serial_data" internal="rx_serial_data" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_phy_inst.rx_is_lockedtodata"
+ name="rx_parallel_data"
+ internal="transceiver_phy_inst.rx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
</interface>
<interface
- name="tx_coreclkin"
- internal="transceiver_phy_inst.tx_coreclkin"
+ name="rx_pma_clkout"
+ internal="transceiver_phy_inst.rx_pma_clkout"
type="conduit"
dir="end">
- <port name="tx_coreclkin" internal="tx_coreclkin" />
+ <port name="rx_pma_clkout" internal="rx_pma_clkout" />
</interface>
<interface
- name="rx_coreclkin"
- internal="transceiver_phy_inst.rx_coreclkin"
+ name="rx_pma_div_clkout"
+ internal="transceiver_phy_inst.rx_pma_div_clkout"
type="conduit"
dir="end">
- <port name="rx_coreclkin" internal="rx_coreclkin" />
+ <port name="rx_pma_div_clkout" internal="rx_pma_div_clkout" />
</interface>
<interface
- name="tx_clkout"
- internal="transceiver_phy_inst.tx_clkout"
+ name="rx_serial_data"
+ internal="transceiver_phy_inst.rx_serial_data"
type="conduit"
dir="end">
- <port name="tx_clkout" internal="tx_clkout" />
+ <port name="rx_serial_data" internal="rx_serial_data" />
</interface>
<interface
- name="rx_clkout"
- internal="transceiver_phy_inst.rx_clkout"
+ name="tx_analogreset"
+ internal="transceiver_phy_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_clkout" internal="rx_clkout" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="tx_parallel_data"
- internal="transceiver_phy_inst.tx_parallel_data"
+ name="tx_cal_busy"
+ internal="transceiver_phy_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="tx_parallel_data" internal="tx_parallel_data" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="tx_control"
- internal="transceiver_phy_inst.tx_control"
+ name="tx_clkout"
+ internal="transceiver_phy_inst.tx_clkout"
type="conduit"
dir="end">
- <port name="tx_control" internal="tx_control" />
+ <port name="tx_clkout" internal="tx_clkout" />
</interface>
<interface
- name="tx_err_ins"
- internal="transceiver_phy_inst.tx_err_ins"
+ name="tx_control"
+ internal="transceiver_phy_inst.tx_control"
type="conduit"
dir="end">
- <port name="tx_err_ins" internal="tx_err_ins" />
+ <port name="tx_control" internal="tx_control" />
</interface>
<interface
- name="unused_tx_parallel_data"
- internal="transceiver_phy_inst.unused_tx_parallel_data"
+ name="tx_coreclkin"
+ internal="transceiver_phy_inst.tx_coreclkin"
type="conduit"
dir="end">
- <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
</interface>
<interface
- name="unused_tx_control"
- internal="transceiver_phy_inst.unused_tx_control"
+ name="tx_digitalreset"
+ internal="transceiver_phy_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="unused_tx_control" internal="unused_tx_control" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_parallel_data"
- internal="transceiver_phy_inst.rx_parallel_data"
+ name="tx_enh_data_valid"
+ internal="transceiver_phy_inst.tx_enh_data_valid"
type="conduit"
dir="end">
- <port name="rx_parallel_data" internal="rx_parallel_data" />
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
</interface>
<interface
- name="rx_control"
- internal="transceiver_phy_inst.rx_control"
+ name="tx_err_ins"
+ internal="transceiver_phy_inst.tx_err_ins"
type="conduit"
dir="end">
- <port name="rx_control" internal="rx_control" />
+ <port name="tx_err_ins" internal="tx_err_ins" />
</interface>
<interface
- name="unused_rx_parallel_data"
- internal="transceiver_phy_inst.unused_rx_parallel_data"
+ name="tx_parallel_data"
+ internal="transceiver_phy_inst.tx_parallel_data"
type="conduit"
dir="end">
- <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
</interface>
<interface
- name="unused_rx_control"
- internal="transceiver_phy_inst.unused_rx_control"
+ name="tx_pma_clkout"
+ internal="transceiver_phy_inst.tx_pma_clkout"
type="conduit"
dir="end">
- <port name="unused_rx_control" internal="unused_rx_control" />
+ <port name="tx_pma_clkout" internal="tx_pma_clkout" />
</interface>
<interface
- name="tx_enh_data_valid"
- internal="transceiver_phy_inst.tx_enh_data_valid"
+ name="tx_pma_div_clkout"
+ internal="transceiver_phy_inst.tx_pma_div_clkout"
type="conduit"
dir="end">
- <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
</interface>
<interface
- name="rx_enh_data_valid"
- internal="transceiver_phy_inst.rx_enh_data_valid"
+ name="tx_serial_clk0"
+ internal="transceiver_phy_inst.tx_serial_clk0"
type="conduit"
dir="end">
- <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
</interface>
<interface
- name="rx_enh_blk_lock"
- internal="transceiver_phy_inst.rx_enh_blk_lock"
+ name="tx_serial_data"
+ internal="transceiver_phy_inst.tx_serial_data"
type="conduit"
dir="end">
- <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ <port name="tx_serial_data" internal="tx_serial_data" />
</interface>
<interface
- name="tx_pma_div_clkout"
- internal="transceiver_phy_inst.tx_pma_div_clkout"
+ name="unused_rx_control"
+ internal="transceiver_phy_inst.unused_rx_control"
type="conduit"
dir="end">
- <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
+ <port name="unused_rx_control" internal="unused_rx_control" />
</interface>
<interface
- name="tx_pma_clkout"
- internal="transceiver_phy_inst.tx_pma_clkout"
+ name="unused_rx_parallel_data"
+ internal="transceiver_phy_inst.unused_rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_pma_clkout" internal="tx_pma_clkout" />
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
</interface>
<interface
- name="rx_pma_clkout"
- internal="transceiver_phy_inst.rx_pma_clkout"
+ name="unused_tx_control"
+ internal="transceiver_phy_inst.unused_tx_control"
type="conduit"
dir="end">
- <port name="rx_pma_clkout" internal="rx_pma_clkout" />
+ <port name="unused_tx_control" internal="unused_tx_control" />
</interface>
<interface
- name="rx_pma_div_clkout"
- internal="transceiver_phy_inst.rx_pma_div_clkout"
+ name="unused_tx_parallel_data"
+ internal="transceiver_phy_inst.unused_tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_pma_div_clkout" internal="rx_pma_div_clkout" />
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
</interface>
<module
+ name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_phy_inst"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115U3F45I2LG" />
- <parameter name="design_environment" value="NATIVE" />
- <parameter name="message_level" value="error" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="protocol_mode" value="teng_baser_mode" />
- <parameter name="pma_mode" value="basic" />
- <parameter name="duplex_mode" value="duplex" />
- <parameter name="channels" value="48" />
- <parameter name="set_data_rate" value="10312.5" />
- <parameter name="rcfg_iface_enable" value="0" />
- <parameter name="enable_simple_interface" value="1" />
- <parameter name="enable_split_interface" value="0" />
- <parameter name="set_enable_calibration" value="0" />
- <parameter name="enable_transparent_pcs" value="0" />
- <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
- <parameter name="set_pcs_bonding_master" value="Auto" />
- <parameter name="tx_pma_clk_div" value="1" />
- <parameter name="plls" value="1" />
- <parameter name="pll_select" value="0" />
- <parameter name="enable_port_tx_pma_clkout" value="1" />
- <parameter name="enable_port_tx_pma_div_clkout" value="1" />
- <parameter name="tx_pma_div_clkout_divider" value="66" />
- <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_tx_pma_elecidle" value="0" />
- <parameter name="enable_port_tx_pma_qpipullup" value="0" />
- <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
- <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
- <parameter name="enable_port_tx_pma_rxfound" value="0" />
- <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
- <parameter name="set_cdr_refclk_freq" value="644.531250" />
- <parameter name="rx_ppm_detect_threshold" value="100" />
- <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
- <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
- <parameter name="rx_pma_dfe_fixed_taps" value="3" />
- <parameter name="enable_rx_pma_floatingtap" value="0" />
- <parameter name="enable_ports_adaptation" value="0" />
- <parameter name="enable_port_rx_pma_clkout" value="1" />
- <parameter name="enable_port_rx_pma_div_clkout" value="1" />
- <parameter name="rx_pma_div_clkout_divider" value="66" />
- <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_clkslip" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
- <parameter name="enable_port_rx_is_lockedtodata" value="1" />
- <parameter name="enable_port_rx_is_lockedtoref" value="0" />
- <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
- <parameter name="enable_ports_rx_manual_ppm" value="0" />
- <parameter name="enable_port_rx_signaldetect" value="0" />
- <parameter name="enable_port_rx_seriallpbken" value="0" />
- <parameter name="enable_ports_rx_prbs" value="0" />
- <parameter name="std_pcs_pma_width" value="10" />
- <parameter name="std_low_latency_bypass_enable" value="0" />
- <parameter name="enable_hip" value="0" />
+ <parameter name="channels" value="48" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
- <parameter name="std_tx_pcfifo_mode" value="low_latency" />
- <parameter name="std_rx_pcfifo_mode" value="low_latency" />
- <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
- <parameter name="std_tx_byte_ser_mode" value="Disabled" />
- <parameter name="std_rx_byte_deser_mode" value="Disabled" />
- <parameter name="std_tx_8b10b_enable" value="1" />
- <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
- <parameter name="std_rx_8b10b_enable" value="1" />
- <parameter name="std_rx_rmfifo_mode" value="disabled" />
- <parameter name="std_rx_rmfifo_pattern_n" value="0" />
- <parameter name="std_rx_rmfifo_pattern_p" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
- <parameter name="pcie_rate_match" value="Bypass" />
- <parameter name="std_tx_bitslip_enable" value="0" />
- <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
- <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
- <parameter name="std_rx_word_aligner_pattern_len" value="7" />
- <parameter name="std_rx_word_aligner_pattern" value="124" />
- <parameter name="std_rx_word_aligner_rknumber" value="3" />
- <parameter name="std_rx_word_aligner_renumber" value="3" />
- <parameter name="std_rx_word_aligner_rgnumber" value="3" />
- <parameter name="std_rx_word_aligner_rvnumber" value="0" />
- <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
- <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
- <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
- <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
- <parameter name="enable_port_rx_std_bitslip" value="0" />
- <parameter name="std_tx_bitrev_enable" value="0" />
- <parameter name="std_tx_byterev_enable" value="0" />
- <parameter name="std_tx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_polinv" value="0" />
- <parameter name="std_rx_bitrev_enable" value="0" />
- <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
- <parameter name="std_rx_byterev_enable" value="0" />
- <parameter name="enable_port_rx_std_byterev_ena" value="0" />
- <parameter name="std_rx_polinv_enable" value="0" />
- <parameter name="enable_port_rx_polinv" value="0" />
- <parameter name="enable_port_rx_std_signaldetect" value="0" />
- <parameter name="enable_ports_pipe_sw" value="0" />
- <parameter name="enable_ports_pipe_hclk" value="0" />
- <parameter name="enable_ports_pipe_g3_analog" value="0" />
- <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
<parameter name="enable_port_pipe_rx_polarity" value="0" />
- <parameter name="enh_pcs_pma_width" value="32" />
- <parameter name="enh_pld_pcs_width" value="66" />
- <parameter name="enh_low_latency_enable" value="0" />
- <parameter name="enh_rxtxfifo_double_width" value="0" />
- <parameter name="enh_txfifo_mode" value="Phase compensation" />
- <parameter name="enh_txfifo_pfull" value="11" />
- <parameter name="enh_txfifo_pempty" value="2" />
- <parameter name="enable_port_tx_enh_fifo_full" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
- <parameter name="enh_rxfifo_mode" value="10GBase-R" />
- <parameter name="enh_rxfifo_pfull" value="23" />
- <parameter name="enh_rxfifo_pempty" value="2" />
- <parameter name="enh_rxfifo_align_del" value="0" />
- <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
<parameter name="enable_port_rx_enh_data_valid" value="1" />
- <parameter name="enable_port_rx_enh_fifo_full" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
<parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
<parameter name="enable_port_rx_enh_fifo_del" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="0" />
<parameter name="enable_port_rx_enh_fifo_insert" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
<parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
- <parameter name="enh_tx_frmgen_enable" value="0" />
- <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
- <parameter name="enh_tx_frmgen_burst_enable" value="0" />
- <parameter name="enable_port_tx_enh_frame" value="0" />
- <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
- <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
- <parameter name="enh_rx_frmsync_enable" value="0" />
- <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enable_port_rx_enh_frame" value="0" />
- <parameter name="enable_port_rx_enh_frame_lock" value="0" />
<parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
- <parameter name="enh_tx_crcgen_enable" value="0" />
- <parameter name="enh_tx_crcerr_enable" value="0" />
- <parameter name="enh_rx_crcchk_enable" value="0" />
- <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
<parameter name="enable_port_rx_enh_highber" value="0" />
<parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
- <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
- <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="0" />
+ <parameter name="enable_port_rx_pma_clkout" value="1" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="1" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="0" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="1" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="0" />
+ <parameter name="enable_rx_pma_floatingtap" value="0" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
<parameter name="enh_rx_64b66b_enable" value="1" />
- <parameter name="enh_tx_sh_err" value="0" />
- <parameter name="enh_tx_scram_enable" value="1" />
- <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
<parameter name="enh_rx_descram_enable" value="1" />
- <parameter name="enh_tx_dispgen_enable" value="0" />
<parameter name="enh_rx_dispchk_enable" value="0" />
- <parameter name="enh_rx_blksync_enable" value="1" />
- <parameter name="enable_port_rx_enh_blk_lock" value="1" />
- <parameter name="enh_tx_bitslip_enable" value="0" />
- <parameter name="enh_tx_polinv_enable" value="0" />
- <parameter name="enh_rx_bitslip_enable" value="0" />
- <parameter name="enh_rx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_enh_bitslip" value="0" />
- <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enh_rx_krfec_err_mark_enable" value="0" />
<parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
<parameter name="enh_tx_krfec_burst_err_enable" value="0" />
<parameter name="enh_tx_krfec_burst_err_len" value="1" />
- <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
- <parameter name="pcs_direct_width" value="8" />
- <parameter name="generate_docs" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
<parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="validation_rule_select" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rapid_validate" value="0" />
<parameter name="rcfg_enable" value="0" />
- <parameter name="rcfg_shared" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
- <parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
@@ -465,8 +424,58 @@
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="66" />
+ <parameter name="rx_ppm_detect_threshold" value="100" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="1" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
+ <parameter name="std_rx_word_aligner_pattern" value="124" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="1" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="66" />
+ <parameter name="validation_rule_select" value="" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys b/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
index 178dcd50d049ed26b0da055b7c05aa09a3743736..a6ef6e778bfbaa16d028912a2d98fca1f97b5b64 100644
--- a/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
+++ b/libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
@@ -6,19 +6,29 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_pll_inst
{
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@@ -36,18 +46,25 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="pll_powerdown"
- internal="transceiver_pll_inst.pll_powerdown"
+ name="mcgb_rst"
+ internal="transceiver_pll_inst.mcgb_rst"
type="conduit"
dir="end">
- <port name="pll_powerdown" internal="pll_powerdown" />
+ <port name="mcgb_rst" internal="mcgb_rst" />
</interface>
<interface
- name="pll_refclk0"
- internal="transceiver_pll_inst.pll_refclk0"
- type="clock"
+ name="mcgb_serial_clk"
+ internal="transceiver_pll_inst.mcgb_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="transceiver_pll_inst.pll_cal_busy"
+ type="conduit"
dir="end">
- <port name="pll_refclk0" internal="pll_refclk0" />
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
@@ -57,98 +74,85 @@
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
- name="pll_cal_busy"
- internal="transceiver_pll_inst.pll_cal_busy"
+ name="pll_powerdown"
+ internal="transceiver_pll_inst.pll_powerdown"
type="conduit"
dir="end">
- <port name="pll_cal_busy" internal="pll_cal_busy" />
+ <port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="mcgb_rst"
- internal="transceiver_pll_inst.mcgb_rst"
- type="conduit"
+ name="pll_refclk0"
+ internal="transceiver_pll_inst.pll_refclk0"
+ type="clock"
dir="end">
- <port name="mcgb_rst" internal="mcgb_rst" />
- </interface>
- <interface
- name="mcgb_serial_clk"
- internal="transceiver_pll_inst.mcgb_serial_clk"
- type="hssi_serial_clock"
- dir="start">
- <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ <port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<module
+ name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_pll_inst"
autoexport="1">
- <parameter name="rcfg_debug" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_fractional" value="0" />
+ <parameter name="enable_hfreq_clk" value="1" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_mcgb" value="1" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
- <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" />
- <parameter name="generate_docs" value="1" />
- <parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="test_mode" value="0" />
- <parameter name="enable_pld_atx_cal_busy_port" value="1" />
- <parameter name="enable_debug_ports_parameters" value="0" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="message_level" value="error" />
- <parameter name="prot_mode" value="Basic" />
- <parameter name="bw_sel" value="low" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="silicon_rev" value="false" />
- <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
- <parameter name="enable_8G_path" value="0" />
- <parameter name="enable_16G_path" value="0" />
- <parameter name="enable_pcie_clk" value="0" />
- <parameter name="enable_cascade_out" value="0" />
- <parameter name="enable_hip_cal_done_port" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
<parameter name="select_manual_config" value="0" />
- <parameter name="set_output_clock_frequency" value="5156.25" />
- <parameter name="enable_fractional" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
- <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
<parameter name="set_ref_clk_div" value="1" />
- <parameter name="set_l_counter" value="2" />
- <parameter name="set_k_counter" value="1" />
- <parameter name="enable_mcgb" value="1" />
- <parameter name="mcgb_div" value="1" />
- <parameter name="enable_hfreq_clk" value="1" />
- <parameter name="enable_mcgb_pcie_clksw" value="0" />
- <parameter name="mcgb_aux_clkin_cnt" value="0" />
- <parameter name="enable_bonding_clks" value="0" />
- <parameter name="enable_fb_comp_bonding" value="0" />
- <parameter name="pma_width" value="64" />
- <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
- <parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index b6d273314a661ba0b7517290f850303a4f441f64..2745c853e92a388c8dbea0bf3c992fb885daebe9 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -30,22 +30,22 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_pll_10g
#vlib ./work/ ;# Assume library work already exists
-vmap ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140 ./work/
+vmap ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141 ./work/
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
-vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_140/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/twentynm_xcvr_avmm.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/a10_avmm_h.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_native_avmm_nf.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/altera_xcvr_atx_pll_a10.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/a10_xcvr_atx_pll.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
+vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_141/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -work ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
vcom "$IP_DIR/ip_arria10_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index cbfea2f40e9bea347cce251e3211cae24a92afa5..5474ddf598df3954f93eb79a98f78b75dd98ba1c 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_140
+hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_141
hdl_lib_uses =
hdl_lib_technology = ip_arria10
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
index a6a3843d48f739d2970e5b446fb7f268d11a936c..f7a6752c1a5bfbecaa6e2536d115c0aa7012b40f 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys
@@ -6,11 +6,16 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element xcvr_atx_pll_a10_0
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -40,6 +45,20 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
<interface
name="pll_powerdown"
internal="xcvr_atx_pll_a10_0.pll_powerdown"
@@ -61,92 +80,72 @@
dir="start">
<port name="tx_serial_clk" internal="tx_serial_clk" />
</interface>
- <interface
- name="pll_locked"
- internal="xcvr_atx_pll_a10_0.pll_locked"
- type="conduit"
- dir="end">
- <port name="pll_locked" internal="pll_locked" />
- </interface>
- <interface
- name="pll_cal_busy"
- internal="xcvr_atx_pll_a10_0.pll_cal_busy"
- type="conduit"
- dir="end">
- <port name="pll_cal_busy" internal="pll_cal_busy" />
- </interface>
<module
+ name="xcvr_atx_pll_a10_0"
kind="altera_xcvr_atx_pll_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="xcvr_atx_pll_a10_0"
autoexport="1">
- <parameter name="rcfg_debug" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_fractional" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
- <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" />
- <parameter name="generate_docs" value="1" />
- <parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="Unknown" />
- <parameter name="test_mode" value="0" />
- <parameter name="enable_pld_atx_cal_busy_port" value="1" />
- <parameter name="enable_debug_ports_parameters" value="0" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="message_level" value="error" />
- <parameter name="prot_mode" value="Basic" />
- <parameter name="bw_sel" value="low" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="silicon_rev" value="false" />
- <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
- <parameter name="enable_8G_path" value="1" />
- <parameter name="enable_16G_path" value="0" />
- <parameter name="enable_pcie_clk" value="0" />
- <parameter name="enable_cascade_out" value="0" />
- <parameter name="enable_hip_cal_done_port" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
<parameter name="select_manual_config" value="0" />
- <parameter name="set_output_clock_frequency" value="5156.25" />
- <parameter name="enable_fractional" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
- <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
<parameter name="set_ref_clk_div" value="1" />
- <parameter name="set_l_counter" value="2" />
- <parameter name="set_k_counter" value="1" />
- <parameter name="enable_mcgb" value="0" />
- <parameter name="mcgb_div" value="1" />
- <parameter name="enable_hfreq_clk" value="0" />
- <parameter name="enable_mcgb_pcie_clksw" value="0" />
- <parameter name="mcgb_aux_clkin_cnt" value="0" />
- <parameter name="enable_bonding_clks" value="0" />
- <parameter name="enable_fb_comp_bonding" value="0" />
- <parameter name="pma_width" value="64" />
- <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
- <parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="0" />
- <parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index 1fb33d8528cf7dc4110ade573f317849b1570e0b..659cce8f3ea693560e544744b9d8ef25d05aadb5 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -30,14 +30,14 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/transceiver_reset_c
#vlib ./work/ ;# Assume library work already exists
-vmap ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140 ./work/
+vmap ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141 ./work/
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
-vlog -sv "$IP_DIR/../altera_xcvr_reset_control_140/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_functions.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_resync.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/altera_xcvr_reset_control.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
+vlog -sv "$IP_DIR/../altera_xcvr_reset_control_141/sim/mentor/alt_xcvr_reset_counter.sv" -work ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
vcom "$IP_DIR/ip_arria10_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 9dc30b52be5e5b2c8675df35638b7697213050e0..2075b80c643cefefc52571f0115f153b3bbff582 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -1,5 +1,5 @@
hdl_lib_name = ip_arria10_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_140
+hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_141
hdl_lib_uses =
hdl_lib_technology = ip_arria10
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
index 8e6724d8f7df6c090f503010b489085158c62b78..a638757ec99addd3bb1964268ce4d7d0dc4d1470 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element xcvr_reset_control_0
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="Unknown" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -48,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="xcvr_reset_control_0.reset"
- type="reset"
+ name="pll_locked"
+ internal="xcvr_reset_control_0.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="xcvr_reset_control_0.tx_analogreset"
+ name="pll_select"
+ internal="xcvr_reset_control_0.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="xcvr_reset_control_0.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="xcvr_reset_control_0.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="xcvr_reset_control_0.tx_ready"
+ name="rx_analogreset"
+ internal="xcvr_reset_control_0.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="xcvr_reset_control_0.pll_locked"
+ name="rx_cal_busy"
+ internal="xcvr_reset_control_0.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="xcvr_reset_control_0.pll_select"
+ name="rx_digitalreset"
+ internal="xcvr_reset_control_0.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="xcvr_reset_control_0.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="xcvr_reset_control_0.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="xcvr_reset_control_0.rx_analogreset"
+ name="rx_ready"
+ internal="xcvr_reset_control_0.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="xcvr_reset_control_0.rx_digitalreset"
+ name="tx_analogreset"
+ internal="xcvr_reset_control_0.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="xcvr_reset_control_0.rx_ready"
+ name="tx_cal_busy"
+ internal="xcvr_reset_control_0.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="xcvr_reset_control_0.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="xcvr_reset_control_0.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="xcvr_reset_control_0.rx_cal_busy"
+ name="tx_ready"
+ internal="xcvr_reset_control_0.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="xcvr_reset_control_0"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="xcvr_reset_control_0"
autoexport="1">
<parameter name="CHANNELS" value="1" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="156" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="0" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
index d6cafd5a1eb5b5cdf28a9d030508b49223d94672..77645e5aa18f13c091b7837da53b0a0a58844f4c 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_reset_controller_inst
{
@@ -48,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="transceiver_reset_controller_inst.reset"
- type="reset"
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="transceiver_reset_controller_inst.tx_analogreset"
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_reset_controller_inst.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="transceiver_reset_controller_inst.tx_ready"
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="transceiver_reset_controller_inst.pll_locked"
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="transceiver_reset_controller_inst.pll_select"
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_reset_controller_inst.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_reset_controller_inst.rx_analogreset"
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_reset_controller_inst.rx_digitalreset"
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="transceiver_reset_controller_inst.rx_ready"
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_reset_controller_inst.rx_cal_busy"
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_reset_controller_inst"
autoexport="1">
<parameter name="CHANNELS" value="1" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="200" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
index d8e66067cf7c7c70975ca9e59197988e234df199..dbb6a65ab903278f66f0485d8271b1ba286fdea4 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/ip_arria10_transceiver_reset_controller_48.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_reset_controller_inst
{
@@ -23,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@@ -48,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="transceiver_reset_controller_inst.reset"
- type="reset"
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="transceiver_reset_controller_inst.tx_analogreset"
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_reset_controller_inst.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="transceiver_reset_controller_inst.tx_ready"
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="transceiver_reset_controller_inst.pll_locked"
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="transceiver_reset_controller_inst.pll_select"
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_reset_controller_inst.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_reset_controller_inst.rx_analogreset"
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_reset_controller_inst.rx_digitalreset"
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="transceiver_reset_controller_inst.rx_ready"
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_reset_controller_inst.rx_cal_busy"
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_reset_controller_inst"
autoexport="1">
<parameter name="CHANNELS" value="48" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="200" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
index d8e66067cf7c7c70975ca9e59197988e234df199..dbb6a65ab903278f66f0485d8271b1ba286fdea4 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/transceiver_reset_controller_48.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_reset_controller_inst
{
@@ -23,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
@@ -48,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="transceiver_reset_controller_inst.reset"
- type="reset"
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="transceiver_reset_controller_inst.tx_analogreset"
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_reset_controller_inst.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="transceiver_reset_controller_inst.tx_ready"
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="transceiver_reset_controller_inst.pll_locked"
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="transceiver_reset_controller_inst.pll_select"
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_reset_controller_inst.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_reset_controller_inst.rx_analogreset"
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_reset_controller_inst.rx_digitalreset"
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="transceiver_reset_controller_inst.rx_ready"
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_reset_controller_inst.rx_cal_busy"
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_reset_controller_inst"
autoexport="1">
<parameter name="CHANNELS" value="48" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="200" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>