From b948db5c0d311851f01a7d58bf6d51bce25ff5e8 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 27 Jul 2018 13:05:02 +0000
Subject: [PATCH] Updated arts_unb2b_sc3 such that it compiles in ModelSim. .
Completed data path from inputs to outputs through all stages. Updated
arts_unb2b_sc3 such that it compiles in Quartus. . Commented out MMM due to
QSYS IP issues . Added IP for 3-channel 10GbE base-R (all mods in technology
dir) . Added g_direction generic to unb2b_board_10gbe in anticipation of
having to split up the now duplex I/O to . the RX part in the input stage
. the TX part in the output stage
---
.../arts/designs/arts_unb2b_sc3/hdllib.cfg | 18 +-
.../src/vhdl/arts_unb2b_sc3.vhd | 468 +++++++------
.../src/vhdl/arts_unb2b_sc3_input.vhd | 516 ++++++++++----
.../src/vhdl/arts_unb2b_sc3_mm_master.vhd | 5 +-
.../src/vhdl/arts_unb2b_sc3_output.vhd | 199 +++++-
.../src/vhdl/arts_unb2b_sc3_processing.vhd | 89 ++-
.../src/vhdl/unb2_board_10gbe.vhd | 2 +
libraries/technology/10gbase_r/hdllib.cfg | 5 +
.../10gbase_r/tech_10gbase_r_arria10_e1sg.vhd | 82 ++-
.../tech_10gbase_r_component_pkg.vhd | 74 +++
.../phy_10gbase_r_3/compile_ip.tcl | 35 +
.../phy_10gbase_r_3/generate_ip.sh | 44 ++
.../phy_10gbase_r_3/hdllib.cfg | 19 +
.../ip_arria10_e1sg_phy_10gbase_r_3.qsys | 628 ++++++++++++++++++
.../compile_ip.tcl | 34 +
.../generate_ip.sh | 44 ++
.../transceiver_reset_controller_3/hdllib.cfg | 19 +
...0_e1sg_transceiver_reset_controller_3.qsys | 175 +++++
18 files changed, 2068 insertions(+), 388 deletions(-)
create mode 100644 libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
create mode 100644 libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
create mode 100755 libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
create mode 100644 libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
create mode 100644 libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
diff --git a/applications/arts/designs/arts_unb2b_sc3/hdllib.cfg b/applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
index 369c5aa3e1..ca9b1d5b0a 100644
--- a/applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
+++ b/applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = arts_unb2b_sc3
hdl_library_clause_name = arts_unb2b_sc3_lib
-hdl_lib_uses_synth = common technology mm unb2b_board unb2b_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g arts_unb1_sc4
+hdl_lib_uses_synth = common technology mm unb2b_board unb2b_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g arts_unb1_sc4 apertif arts_tab_beamformer iquv
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip =
@@ -11,12 +11,14 @@ hdl_lib_include_ip =
ip_arria10_e1sg_transceiver_pll_10g
ip_arria10_e1sg_phy_10gbase_r
+ ip_arria10_e1sg_phy_10gbase_r_3
ip_arria10_e1sg_phy_10gbase_r_4
ip_arria10_e1sg_phy_10gbase_r_12
ip_arria10_e1sg_phy_10gbase_r_24
ip_arria10_e1sg_phy_10gbase_r_48
ip_arria10_e1sg_transceiver_reset_controller_1
+ ip_arria10_e1sg_transceiver_reset_controller_3
ip_arria10_e1sg_transceiver_reset_controller_4
ip_arria10_e1sg_transceiver_reset_controller_12
ip_arria10_e1sg_transceiver_reset_controller_24
@@ -25,13 +27,19 @@ hdl_lib_include_ip =
synth_files =
src/vhdl/qsys_arts_unb2b_sc3_pkg.vhd
src/vhdl/arts_unb2b_sc3_mm_master.vhd
- # src/vhdl/arts_unb2b_sc3_input.vhd
- # src/vhdl/arts_unb2b_sc3_processing.vhd
- # src/vhdl/arts_unb2b_sc3_output.vhd
+ src/vhdl/arts_unb2b_sc3_input.vhd
+ src/vhdl/arts_unb2b_sc3_processing.vhd
+ # Workaround; we can't use unb1 libs in unb2b Questasim (yet).
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
+ src/vhdl/arts_unb2b_sc3_output.vhd
src/vhdl/arts_unb2b_sc3.vhd
test_bench_files =
- tb/vhdl/tb_arts_unb2b_sc3.vhd
+# tb/vhdl/tb_arts_unb2b_sc3.vhd
[modelsim_project_file]
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
index ec9178ba5f..61ed63c6e6 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
@@ -110,32 +110,31 @@ ENTITY arts_unb2b_sc3 IS
MB_I_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_I
MB_II_REF_CLK : IN STD_LOGIC := '0'; -- Reference clock for MB_II
-
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC := '0';
-- front transceivers
- --QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Input
- --QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-
- --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- --QSFP_RST : INOUT STD_LOGIC;
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 0..3
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Outputs 0..3
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 4..7
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Outputs 4..7
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 8..11
+ QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 12..15
+ QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 16..19
+ QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Inputs 20..23
+ QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_RST : INOUT STD_LOGIC;
-- Leds
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0) --2 LEDs per QSFP so not usable in quad 10G mode
);
END arts_unb2b_sc3;
@@ -145,22 +144,42 @@ ARCHITECTURE str OF arts_unb2b_sc3 IS
-------------------------------------------------------------------------------
-- ARTS SC3 constants
-------------------------------------------------------------------------------
- CONSTANT c_nof_dishes : NATURAL := 8; -- Equidistant dishes RT2..RT9
- CONSTANT c_nof_tabs : NATURAL := 9; -- 9 instead of 12 (SC4) to match Arria10 resources
- CONSTANT c_nof_cbsets : NATURAL := 8; -- Matches the number of processing FPGAs/UniBoard in SC4
- CONSTANT c_data_w : NATURAL := 9; -- 9b complex input data
- CONSTANT c_weights_w : NATURAL := 8; -- 8b complex weigths
- CONSTANT c_nof_beamlets : NATURAL := 120; -- 960 Beamlets in 6b mode, 88 Beamlets in 8b mode
- CONSTANT c_nof_cb : NATURAL := 40; -- 40 Compound Beams = number of GPU cluster nodes
- CONSTANT c_nof_channels_in : NATURAL := 64; -- 64 channels per timesamples coming from XC
- CONSTANT c_nof_channels_out : NATURAL := 4; -- 4 channels per timesample at the IQUV output
- CONSTANT c_iquv_nof_int : NATURAL := c_nof_channels_in/c_nof_channels_out; --16
- CONSTANT c_iquv_data_w_out : NATURAL := 8; -- 8b Stokes parameters
+ CONSTANT c_nof_cbsets : NATURAL := 1; -- Matches the number of processing FPGAs/UniBoard in SC4
+ CONSTANT c_nof_dishes : NATURAL := 8; -- Equidistant dishes RT2..RT9
+ CONSTANT c_nof_tabs : NATURAL := 9; -- 9 instead of 12 (SC4) to match Arria10 resources
+ CONSTANT c_data_w : NATURAL := 9; -- 9b complex input data
+ CONSTANT c_weights_w : NATURAL := 9; -- 9b complex weigths
+ CONSTANT c_nof_beamlets : NATURAL := 120; -- 960 Beamlets in 6b mode, 88 Beamlets in 8b mode
+ CONSTANT c_nof_cb_per_set : NATURAL := 5; -- 40 Compound Beams in total = number of GPU cluster nodes
+ CONSTANT c_nof_subbands_per_cb : NATURAL := 24; -- 120 beamlets / 5 CB
+ CONSTANT c_nof_channels_in : NATURAL := 64; -- 64 channels per timesamples coming from XC
+ CONSTANT c_nof_channels_out : NATURAL := 4; -- 4 channels per timesample at the IQUV output
+ CONSTANT c_iquv_nof_int : NATURAL := c_nof_channels_in/c_nof_channels_out; --16
+ CONSTANT c_iquv_data_w_out : NATURAL := 8; -- 8b Stokes parameters
+ CONSTANT c_nof_timesamples : NATURAL := 12500;
-------------------------------------------------------------------------------
-- arts_unb2b_sc3_input
-------------------------------------------------------------------------------
- SIGNAL arts_unb2b_sc3_input_src_out_2arr : t_dp_sosi_2arr_8(c_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
+ SIGNAL arts_unb2b_sc3_input_src_out_2arr_8 : t_dp_sosi_2arr_8(c_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
+ SIGNAL general_bsn_arr : t_slv_64_arr(c_nof_cbsets-1 DOWNTO 0);
+
+ SIGNAL reg_dp_bsn_align_mosi : t_mem_mosi;
+ SIGNAL reg_dp_bsn_align_miso : t_mem_miso;
+
+ -------------------------------------------------------------------------------
+ -- arts_unb2b_sc3_processing
+ -------------------------------------------------------------------------------
+ SIGNAL arts_unb2b_sc3_processing_src_out_2arr_9 : t_dp_sosi_2arr_9(c_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
+
+ SIGNAL ram_arts_tab_beamformer_mosi : t_mem_mosi; --FIXME connect in QSYS
+ SIGNAL ram_arts_tab_beamformer_miso : t_mem_miso := c_mem_miso_rst;
+
+ -------------------------------------------------------------------------------
+ -- arts_unb2b_sc3_output:
+ -------------------------------------------------------------------------------
+ SIGNAL arts_unb2b_sc3_output_src_out_arr : t_dp_sosi_arr(c_nof_cbsets-1 DOWNTO 0); --8 CB sets, 1 CB set per output 10GbE fiber
+ SIGNAL arts_unb2b_sc3_output_src_in_arr : t_dp_siso_arr(c_nof_cbsets-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- ctrl_unb2_board
@@ -247,186 +266,239 @@ BEGIN
-- . [ 8 CB sets * 3 10G ] * [ packed data ]
-- (<--- 24 streams --->) * (<-- 9 Gbps -->)
-- (<--- 24 streams * 9 Gbps = 216 Gbps -->)
- -- . Output : arts_unb2b_sc3_input_src_out_2arr ($10.2 - Equation 101):
+ -- . Output : arts_unb2b_sc3_input_src_out_2arr_8 ($10.2 - Equation 101):
-- . [8 CB sets * 8 dishes] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<--- 64 streams --->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------->)
-- (<-------------------------- 64 streams * 3.375 Gbps = 216 Gbps ----------------------------->)
+ -- . TODO: Keep an eye on the resource usage of these 24 (!) 10GbE MACs!
-------------------------------------------------------------------------------
- --u_arts_unb2b_sc3_input : ENTITY work.arts_unb2b_sc3_input
- --GENERIC MAP (
- -- g_sim => g_sim,
- -- g_nof_cbsets => c_nof_cbsets
- --)
- --PORT MAP (
- -- SA_CLK => SA_CLK,
-
- -- QSFP_0_RX => QSFP_0_RX,
- -- QSFP_0_TX => QSFP_0_TX,
- -- QSFP_1_RX => QSFP_1_RX,
- -- QSFP_1_TX => QSFP_1_TX,
- -- QSFP_2_RX => QSFP_2_RX,
- -- QSFP_2_TX => QSFP_2_TX,
- -- QSFP_3_RX => QSFP_3_RX,
- -- QSFP_3_TX => QSFP_3_TX,
- -- QSFP_4_RX => QSFP_4_RX,
- -- QSFP_4_TX => QSFP_4_TX,
- -- QSFP_5_RX => QSFP_5_RX,
- -- QSFP_5_TX => QSFP_5_TX,
-
- -- QSFP_SDA => QSFP_SDA,
- -- QSFP_SCL => QSFP_SCL,
- -- QSFP_RST => QSFP_RST,
- -- QSFP_LED => QSFP_LED,
-
- -- src_out_2arr => arts_unb2b_sc3_input_src_out_2arr
- --);
-
- ---------------------------------------------------------------------------------
- ---- arts_unb2b_sc3_processing:
- ---- . Purpose:
- ---- . Create 9 TABs + integrated Stokes params for 40 Compound Beams
- ---- . Input : arts_unb2b_sc3_input_src_out_2arr ($10.2 - Equation 101):
- ---- . Output: arts_unb2b_sc3_processing_src_out_2arr ($10.7 - Equation 112):
- ---- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
- ---- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
- ---- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
- ---------------------------------------------------------------------------------
- --u_arts_unb2b_sc3_processing : ENTITY work.arts_unb2b_sc3_processing
- --GENERIC MAP (
- -- g_sim => g_sim,
- -- g_nof_dishes => c_nof_dishes,
- -- g_nof_cbsets => c_nof_cbsets,
- -- g_data_w => c_data_w,
- -- g_weights_w => c_weights_w,
- -- g_nof_beamlets => c_nof_beamlets,
- -- g_nof_tabs => c_nof_tabs,
- -- g_iquv_nof_int => c_nof_int_iquv,
- -- g_iquv_data_w_out => c_iquv_data_w_out
- --)
- --PORT MAP (
- -- snk_in_2arr => arts_unb2b_sc3_input_src_out_2arr,
- -- src_out_2arr => arts_unb2b_sc3_processing_src_out_2arr
- --);
-
- ---------------------------------------------------------------------------------
- ---- arts_unb2b_sc3_output:
- ---- . Purpose:
- ---- .
- ---- . Input : arts_unb2b_sc3_processing_src_out_2arr
- ---- . Output:
- ---- . TODO
- ---------------------------------------------------------------------------------
- --u_arts_unb2b_sc3_output : ENTITY work.arts_unb2b_sc3_output
- --GENERIC MAP (
- -- g_sim => g_sim,
- -- g_nof_cbsets => c_nof_cbsets,
- -- g_nof_cb => c_nof_cb,
- -- g_nof_tabs => c_nof_tabs,
- -- g_iquv_data_w_out => c_iquv_data_w_out
- --)
- --PORT MAP (
- -- snk_in_2arr => arts_unb2b_sc3_processing_src_out_2arr,
- -- src_out_arr => arts_unb2b_sc3_output_src_out_arr
- --);
-
- -----------------------------------------------------------------------------
- -- MM master
- -----------------------------------------------------------------------------
- u_arts_unb2b_sc3_mm_master : ENTITY work.arts_unb2b_sc3_mm_master
+ u_arts_unb2b_sc3_input : ENTITY work.arts_unb2b_sc3_input
GENERIC MAP (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_nof_streams_qsfp => c_nof_streams_qsfp,
- g_nof_streams_ring => c_nof_streams_qsfp
- )
- PORT MAP(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ g_sim => g_sim,
+ g_nof_cbsets => c_nof_cbsets
+ )
+ PORT MAP (
+ SA_CLK => SA_CLK,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+ QSFP_RST => QSFP_RST,
+ QSFP_LED => QSFP_LED,
+
+ reg_dp_bsn_align_mosi => reg_dp_bsn_align_mosi,
+ reg_dp_bsn_align_miso => reg_dp_bsn_align_miso,
+
+ src_out_2arr_8 => arts_unb2b_sc3_input_src_out_2arr_8,
+ general_bsn_arr => general_bsn_arr,
+
+ snk_in_arr => arts_unb2b_sc3_output_src_out_arr, -- Not input related; feeds the 10G transmitters
+ snk_out_arr => arts_unb2b_sc3_output_src_in_arr
+ );
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ -------------------------------------------------------------------------------
+ -- arts_unb2b_sc3_processing:
+ -- . Purpose:
+ -- . Create 9 TABs + integrated Stokes params for 40 Compound Beams
+ -- . Input : arts_unb2b_sc3_input_src_out_2arr_8 ($10.2 - Equation 101):
+ -- . Output: arts_unb2b_sc3_processing_src_out_2arr_9 ($10.7 - Equation 112):
+ -- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
+ -- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
+ -- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
+ -------------------------------------------------------------------------------
+ u_arts_unb2b_sc3_processing : ENTITY work.arts_unb2b_sc3_processing
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_nof_dishes => c_nof_dishes,
+ g_nof_cbsets => c_nof_cbsets,
+ g_data_w => 12, --c_data_w, FIXME SC4 uses 12b data, we use 9b. Causes error in tab_beamformer w.r.t quantization.
+ g_weights_w => c_weights_w,
+ g_nof_beamlets => c_nof_beamlets,
+ g_nof_tabs => c_nof_tabs,
+ g_iquv_nof_int => c_iquv_nof_int,
+ g_iquv_data_w_out => c_iquv_data_w_out
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ snk_in_2arr_8 => arts_unb2b_sc3_input_src_out_2arr_8,
+ src_out_2arr_9 => arts_unb2b_sc3_processing_src_out_2arr_9,
- -- 10GbE
- reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
- reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+ ram_arts_tab_beamformer_mosi => ram_arts_tab_beamformer_mosi,
+ ram_arts_tab_beamformer_miso => ram_arts_tab_beamformer_miso
+ );
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso
+ -------------------------------------------------------------------------------
+ -- arts_unb2b_sc3_output:
+ -- . Purpose:
+ -- .
+ -- . Input : arts_unb2b_sc3_processing_src_out_2arr_9
+ -- . Output:
+ -- . TODO
+ -------------------------------------------------------------------------------
+ u_arts_unb2b_sc3_output : ENTITY work.arts_unb2b_sc3_output
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_nof_cbsets => c_nof_cbsets,
+ g_nof_cb_per_set => c_nof_cb_per_set,
+ g_nof_subbands_per_cb => c_nof_subbands_per_cb,
+ g_nof_channels => c_nof_channels_out,
+ g_nof_timesamples => c_nof_timesamples,
+ g_nof_tabs => c_nof_tabs,
+ g_iquv_data_w_out => c_iquv_data_w_out
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in_2arr_9 => arts_unb2b_sc3_processing_src_out_2arr_9,
+ general_bsn_arr => general_bsn_arr,
+
+ src_out_arr => arts_unb2b_sc3_output_src_out_arr,
+ src_in_arr => arts_unb2b_sc3_output_src_in_arr,
+
+ reg_dp_offload_tx_tab_iquv_hdr_dat_mosi => c_mem_mosi_rst,
+ reg_dp_offload_tx_tab_iquv_hdr_dat_miso => OPEN,
+ reg_dp_xonoff_tab_iquv_mosi => c_mem_mosi_rst,
+ reg_dp_xonoff_tab_iquv_miso => OPEN,
+ reg_dp_offload_tx_tab_i_hdr_dat_mosi => c_mem_mosi_rst,
+ reg_dp_offload_tx_tab_i_hdr_dat_miso => OPEN,
+ reg_tab_dest_ip_mosi => c_mem_mosi_rst,
+ reg_tab_dest_ip_miso => OPEN,
+ reg_tab_dest_mac_mosi => c_mem_mosi_rst,
+ reg_tab_dest_mac_miso => OPEN,
+ reg_dp_xonoff_tab_i_mosi => c_mem_mosi_rst,
+ reg_dp_xonoff_tab_i_miso => OPEN,
+
+ ID => ID
);
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+-- u_arts_unb2b_sc3_mm_master : ENTITY work.arts_unb2b_sc3_mm_master
+-- GENERIC MAP (
+-- g_sim => g_sim,
+-- g_sim_unb_nr => g_sim_unb_nr,
+-- g_sim_node_nr => g_sim_node_nr,
+-- g_technology => g_technology,
+-- g_nof_streams_qsfp => c_nof_streams_qsfp,
+-- g_nof_streams_ring => c_nof_streams_qsfp
+-- )
+-- PORT MAP(
+-- mm_rst => mm_rst,
+-- mm_clk => mm_clk,
+--
+-- -- PIOs
+-- pout_wdi => pout_wdi,
+--
+-- -- Manual WDI override
+-- reg_wdi_mosi => reg_wdi_mosi,
+-- reg_wdi_miso => reg_wdi_miso,
+--
+-- -- system_info
+-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+-- reg_unb_system_info_miso => reg_unb_system_info_miso,
+-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+-- rom_unb_system_info_miso => rom_unb_system_info_miso,
+--
+-- -- UniBoard I2C sensors
+-- reg_unb_sens_mosi => reg_unb_sens_mosi,
+-- reg_unb_sens_miso => reg_unb_sens_miso,
+--
+-- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+-- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+--
+-- -- FPGA sensors
+-- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+-- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+-- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+-- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+--
+-- -- PPSH
+-- reg_ppsh_mosi => reg_ppsh_mosi,
+-- reg_ppsh_miso => reg_ppsh_miso,
+--
+-- -- eth1g ch0
+-- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+-- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+-- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+-- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+-- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+-- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+-- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+-- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+--
+-- -- eth1g ch1
+-- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+-- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+-- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+-- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+-- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+-- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+-- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+-- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+--
+-- -- EPCS read
+-- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+-- reg_dpmm_data_miso => reg_dpmm_data_miso,
+-- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+-- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+--
+-- -- EPCS write
+-- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+-- reg_mmdp_data_miso => reg_mmdp_data_miso,
+-- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+-- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+--
+-- -- EPCS status/control
+-- reg_epcs_mosi => reg_epcs_mosi,
+-- reg_epcs_miso => reg_epcs_miso,
+--
+-- -- Remote Update
+-- reg_remu_mosi => reg_remu_mosi,
+-- reg_remu_miso => reg_remu_miso,
+--
+-- -- 10GbE
+-- reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
+-- reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
+--
+-- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+-- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+--
+-- -- eth10g status
+-- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+-- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+-- --TODO add to QSYS
+-- reg_dp_bsn_align_mosi => reg_dp_bsn_align_mosi,
+-- reg_dp_bsn_align_miso => reg_dp_bsn_align_miso
+-- );
+
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_input.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_input.vhd
index cd470192db..1a78c303b3 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_input.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_input.vhd
@@ -57,71 +57,197 @@
-- . [t][5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits]
-- . t = correlator integration interval 1.024s
-- . Each of these 8 sets carry 120 beamlets, for a total of 960 beamlets.
+-- . The snk_in_arr inputs are used to access the 10G transmitters. This is not
+-- part of this input stage (but fed by the output stage).
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, apertif_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE unb2b_board_lib.unb2_board_pkg.ALL;
+USE apertif_lib.apertif_udp_offload_pkg.ALL; --TODO Replace this with arts_unb2b_xc_emu_lib.udp_offload_pkg when available
+USE common_lib.common_field_pkg.ALL;
ENTITY arts_unb2b_sc3_input IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE;
- g_nof_cbsets : NATURAL
+ g_nof_cbsets : NATURAL -- 1..8 where each CBset comes in on 3 fibers
);
PORT (
- -- Front transceivers
- SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
-
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_RST : INOUT STD_LOGIC;
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-
- src_out_2arr : OUT t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0) -- 8 CB sets * 8 dishes
- );
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ QSFP_RST : INOUT STD_LOGIC;
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ reg_dp_bsn_align_mosi : IN t_mem_mosi;
+ reg_dp_bsn_align_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ src_out_2arr_8 : OUT t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
+ general_bsn_arr : OUT t_slv_64_arr(g_nof_cbsets-1 DOWNTO 0);
+
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_cbsets-1 DOWNTO 0); -- Not input related; feeds the 10G transmitters
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_cbsets-1 DOWNTO 0)
+ );
END arts_unb2b_sc3_input;
ARCHITECTURE str OF arts_unb2b_sc3_input IS
+ -------------------------------------------------------------------------------
+ -- Front transceiver I/O and corresponding LEDs
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_fibers_per_cb_set : NATURAL := 3; --3 optical inputs per CB set
+ CONSTANT c_nof_10GbE_streams : NATURAL := g_nof_cbsets*c_nof_fibers_per_cb_set;
+ CONSTANT c_nof_qsfp_bus : NATURAL := ceil_div(c_nof_10GbE_streams, c_unb2_board_tr_qsfp.bus_w);
+
+ SIGNAL unb2_board_front_io_qsfp_tx : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL unb2_board_front_io_qsfp_rx : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+
+ SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus*c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_qsfp_bus*c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ SIGNAL unb2_board_qsfp_leds_tx_snk_in_arr : t_dp_sosi_arr(c_nof_qsfp_bus*c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2_board_qsfp_leds_rx_snk_in_arr : t_dp_sosi_arr(c_nof_qsfp_bus*c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL unb2_board_front_io_qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL unb2_board_front_io_qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+ -------------------------------------------------------------------------------
+ -- 10GbE MAC
+ -------------------------------------------------------------------------------
+ SIGNAL unb2_board_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL unb2_board_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_10gbe_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ -------------------------------------------------------------------------------
+ -- dp_offload_rx
+ -------------------------------------------------------------------------------
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_sosi_rst);
+
+ -------------------------------------------------------------------------------
+ -- BSN Aligner + FIFOs
+ -------------------------------------------------------------------------------
+ CONSTANT c_block_size : NATURAL := 176;
+ CONSTANT c_block_period : NATURAL := c_block_size + 10; -- FIXME Based on....?
+ CONSTANT c_bsn_align_latency : NATURAL := 3;
+ CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
+ CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
+ CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
+ CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
+
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_snk_in_2arr_3 : t_dp_sosi_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_snk_out_2arr_3 : t_dp_siso_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_src_out_2arr_3 : t_dp_sosi_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_src_in_2arr_3 : t_dp_siso_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+
+ SIGNAL reg_dp_bsn_align_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_bsn_align_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+
+ -------------------------------------------------------------------------------
+ -- dp_repack_data
+ -------------------------------------------------------------------------------
+ SIGNAL dp_repack_data_src_out_2arr_3 : t_dp_sosi_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL dp_repack_data_src_in_2arr_3 : t_dp_siso_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+
+ -------------------------------------------------------------------------------
+ -- DP sync checker / insert
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_blk_per_sync : NATURAL := 800000;
+
+ SIGNAL dp_sync_checker_fake_sync_enable : STD_LOGIC := '1'; -- generate an artificial sync during simulation
+
+ SIGNAL dp_sync_checker_snk_in_2arr_3 : t_dp_sosi_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL dp_sync_checker_src_out_2arr_3 : t_dp_sosi_2arr_3(g_nof_cbsets-1 DOWNTO 0);
+
+ -------------------------------------------------------------------------------
+ -- Final output rewiring
+ -------------------------------------------------------------------------------
+ SIGNAL concatenated_144b_sosi_arr : t_dp_sosi_arr(g_nof_cbsets-1 DOWNTO 0);
BEGIN
-------------------------------------------------------------------------------
- -- Wire up the front transceiver I/O and corresponding LEDs
+ -- Front transceiver I/O and corresponding LEDs
+ -- . We have 8 CB sets coming in as 24 optical inputs. Since g_nof_cbsets can
+ -- be 1..8, we round the number of optical inputs up per QSFP (4 inputs)
+ -- as follows:
+ --
+ -- g_nof_cbsets |c_nof_10GbE_streams | c_nof_qsfp_bus
+ -- -------------+-------------------+----------------
+ -- 8 | 24 | 6
+ -- 7 | 21 | 6
+ -- 6 | 18 | 5
+ -- 5 | 15 | 4
+ -- 4 | 12 | 3
+ -- 3 | 9 | 3
+ -- 2 | 6 | 2
+ -- 1 | 3 | 1
+ --
+ -- TODO Make sure to define c_nof_10GbE_streams pins in the TCL pin file,
+ -- (corresponding to g_nof_cbsets for that revision), *not*
+ -- c_nof_qsfp_bus*4 pins.
-------------------------------------------------------------------------------
- unb2_board_front_io_qsfp_rx(0) <= QSFP_0_RX;
- unb2_board_front_io_qsfp_rx(1) <= QSFP_1_RX;
- unb2_board_front_io_qsfp_rx(2) <= QSFP_2_RX;
- unb2_board_front_io_qsfp_rx(3) <= QSFP_3_RX;
- unb2_board_front_io_qsfp_rx(4) <= QSFP_4_RX;
- unb2_board_front_io_qsfp_rx(5) <= QSFP_5_RX;
-
- QSFP_0_TX <= unb2_board_front_io_qsfp_tx(0);
- QSFP_1_TX <= unb2_board_front_io_qsfp_tx(1);
- QSFP_2_TX <= unb2_board_front_io_qsfp_tx(2);
- QSFP_3_TX <= unb2_board_front_io_qsfp_tx(3);
- QSFP_4_TX <= unb2_board_front_io_qsfp_tx(4);
- QSFP_5_TX <= unb2_board_front_io_qsfp_tx(5);
+ gen_qsfp_0: IF c_nof_qsfp_bus>0 GENERATE
+ unb2_board_front_io_qsfp_rx(0) <= QSFP_0_RX;
+ QSFP_0_TX <= unb2_board_front_io_qsfp_tx(0);
+ END GENERATE;
+ gen_qsfp_1: IF c_nof_qsfp_bus>1 GENERATE
+ unb2_board_front_io_qsfp_rx(1) <= QSFP_1_RX;
+ QSFP_1_TX <= unb2_board_front_io_qsfp_tx(1);
+ END GENERATE;
+ gen_qsfp_2: IF c_nof_qsfp_bus>2 GENERATE
+ unb2_board_front_io_qsfp_rx(2) <= QSFP_2_RX;
+ QSFP_2_TX <= unb2_board_front_io_qsfp_tx(2);
+ END GENERATE;
+ gen_qsfp_3: IF c_nof_qsfp_bus>3 GENERATE
+ unb2_board_front_io_qsfp_rx(3) <= QSFP_3_RX;
+ QSFP_3_TX <= unb2_board_front_io_qsfp_tx(3);
+ END GENERATE;
+ gen_qsfp_4: IF c_nof_qsfp_bus>4 GENERATE
+ unb2_board_front_io_qsfp_rx(4) <= QSFP_4_RX;
+ QSFP_4_TX <= unb2_board_front_io_qsfp_tx(4);
+ END GENERATE;
+ gen_qsfp_5: IF c_nof_qsfp_bus>5 GENERATE
+ unb2_board_front_io_qsfp_rx(5) <= QSFP_5_RX;
+ QSFP_5_TX <= unb2_board_front_io_qsfp_tx(5);
+ END GENERATE;
u_unb2_board_front_io : ENTITY unb2b_board_lib.unb2_board_front_io
GENERIC MAP (
@@ -143,7 +269,6 @@ BEGIN
u_unb2_board_qsfp_leds : ENTITY unb2b_board_lib.unb2_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
- g_factory_image => g_factory_image,
g_nof_qsfp => c_nof_qsfp_bus,
g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
)
@@ -161,47 +286,57 @@ BEGIN
-------------------------------------------------------------------------------
-- 10GbE MAC
+ -- FIXME FIXME FIXME g_nof_macs cannot be anything other than 1,4,12 or 24 !!!
+ -- . Note - I added IP for 3 channels (g_nof_macs).
-------------------------------------------------------------------------------
- u_unb2_board_10gbe: ENTITY unb2b_board_10gbe_lib.unb2_board_10gbe --FIXME tr_10GbE is tech independent! We don want this!
+ u_unb2_board_10gbe: ENTITY unb2b_board_10gbe_lib.unb2_board_10gbe --FIXME tr_10GbE is tech independent, We don want this
GENERIC MAP (
g_sim => g_sim,
g_sim_level => 1,
g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size*2
+ g_nof_macs => c_nof_10GbE_streams,
+ g_direction => "TX_RX"
)
PORT MAP (
tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
+
mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi, --FIXME Ring? We don't use the ring!
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi, --FIXME rename this to base_r_mosi
- reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
+ mm_rst => mm_rst,
- dp_rst => dp_rst,
dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+-- TODO: feed this through the entity and connect to MMM
+-- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi, --FIXME Ring? We don't use the ring!
+-- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+-- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+-- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+-- reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
+-- reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,
src_out_arr => unb2_board_10gbe_src_out_arr,
src_in_arr => unb2_board_10gbe_src_in_arr,
snk_out_arr => unb2_board_10gbe_snk_out_arr,
snk_in_arr => unb2_board_10gbe_snk_in_arr,
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_streams-1 DOWNTO 0)
);
+
+ -- 10G TX inputs
+ unb2_board_10gbe_snk_in_arr(g_nof_cbsets-1 DOWNTO 0) <= snk_in_arr;
+ snk_out_arr <= unb2_board_10gbe_snk_out_arr(g_nof_cbsets-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- dp_offload_rx
+ -- . TODO We're using the g_hdr_field_arr of apertif_udp_offload_pkg first.
+ -- Replace this with c_hdr_field arr of arts_unb2b_xc_emu when available.
-----------------------------------------------------------------------------
u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
GENERIC MAP (
g_nof_streams => c_nof_10GbE_streams,
- g_data_w => c_xgmii_data_w,
- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ g_data_w => 64,
+ g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr, --TODO Replace this with c_hdr_field arr of arts_unb2b_xc_emu when available
g_remove_crc => FALSE,
g_crc_nof_words => 0
)
@@ -212,14 +347,11 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ snk_in_arr => unb2_board_10gbe_src_out_arr,
+ snk_out_arr => unb2_board_10gbe_src_in_arr,
src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
hdr_fields_out_arr => hdr_fields_out_arr
);
@@ -228,9 +360,9 @@ BEGIN
dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
- --dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
- dp_offload_rx_restored_src_out_arr(i).re <= dp_offload_rx_src_out_arr(i).re;
- dp_offload_rx_restored_src_out_arr(i).im <= dp_offload_rx_src_out_arr(i).im;
+ dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+-- dp_offload_rx_restored_src_out_arr(i).re(8 DOWNTO 0) <= dp_offload_rx_src_out_arr(i).re(8 DOWNTO 0);
+-- dp_offload_rx_restored_src_out_arr(i).im(8 DOWNTO 0) <= dp_offload_rx_src_out_arr(i).im(8 DOWNTO 0);
dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
@@ -238,36 +370,45 @@ BEGIN
END GENERATE;
-----------------------------------------------------------------------------
- -- BSN alignment + FIFOs (TODO not in sim!)
+ -- BSN alignment + FIFOs
+ -- . Note: 1 FIFO per input fiber
+ -- 1 BSN aligner per CB set
-----------------------------------------------------------------------------
- gen_mms_dp_bsn_align : IF g_sim = FALSE GENERATE
-
gen_dp_fifo_fill: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
- g_data_w => c_xgmii_data_w,
+ g_data_w => 64,
g_bsn_w => c_dp_stream_bsn_w,
g_channel_w => c_dp_stream_channel_w,
g_use_bsn => TRUE,
- g_use_channel => TRUE,
- g_use_error => TRUE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
g_use_sync => TRUE,
- g_use_complex => TRUE,
+ g_use_complex => FALSE,
g_fifo_fill => c_dp_fifo_fill,
g_fifo_size => c_dp_fifo_size
)
PORT MAP (
- rst => dp_rst,
clk => dp_clk,
+ rst => dp_rst,
+ snk_in => dp_offload_rx_restored_src_out_arr(i),
snk_out => dp_offload_rx_src_in_arr(i),
- snk_in => dp_force_src_out_arr(i),
- src_in => dp_fifo_fill_src_in_arr(i),
- src_out => dp_fifo_fill_src_out_arr(i)
+ src_out => dp_fifo_fill_src_out_arr(i),
+ src_in => dp_fifo_fill_src_in_arr(i)
);
END GENERATE;
+ -- Wire flat fiber array [c_nof_10GbE_streams] to 2d array [g_nof_cbsets][3 fibers]
+ gen_dp_bsn_align_snk_in_2arr_3: FOR i IN 0 TO g_nof_cbsets-1 GENERATE
+ gen_j: FOR j IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ dp_bsn_align_snk_in_2arr_3(i)(j) <= dp_fifo_fill_src_out_arr(i*c_nof_10GbE_streams+j);
+ dp_fifo_fill_src_in_arr(i*c_nof_10GbE_streams+j) <= dp_bsn_align_snk_out_2arr_3(i)(j);
+ END GENERATE;
+ END GENERATE;
+
+ gen_mms_dp_bsn_align: FOR i IN 0 TO g_nof_cbsets-1 GENERATE
u_mms_dp_bsn_align : ENTITY dp_lib.mms_dp_bsn_align
GENERIC MAP (
g_block_size => c_block_size,
@@ -279,91 +420,182 @@ BEGIN
g_bsn_request_pipeline => 2
)
PORT MAP (
- dp_rst => dp_rst,
dp_clk => dp_clk,
-
- snk_out_arr => dp_fifo_fill_src_in_arr,
- snk_in_arr => dp_bsn_align_snk_in_arr,
-
- src_in_arr => (OTHERS=>c_dp_siso_rdy),
- src_out_arr => dp_bsn_align_src_out_arr,
+ dp_rst => dp_rst,
- mm_rst => mm_rst,
mm_clk => mm_clk,
-
- reg_mosi => reg_dp_bsn_align_input_mosi,
- reg_miso => reg_dp_bsn_align_input_miso
+ mm_rst => mm_rst,
- -----------------------------------------------------------------------------
- -- RX: BSN monitors (TODO not in sim!)
- -----------------------------------------------------------------------------
- dp_bsn_monitor_input_in_sosi_arr(2 DOWNTO 0) <= dp_force_src_out_arr; --Un-aligned, non-flow controlled input streams
- dp_bsn_monitor_input_in_siso_arr(2 DOWNTO 0) <= (OTHERS=>c_dp_siso_rdy);
+ snk_in_arr => dp_bsn_align_snk_in_2arr_3(i),
+ snk_out_arr => dp_bsn_align_snk_out_2arr_3(i),
+
+ src_in_arr => dp_bsn_align_src_in_2arr_3(i),
+ src_out_arr => dp_bsn_align_src_out_2arr_3(i),
- dp_bsn_monitor_input_in_sosi_arr(5 DOWNTO 3) <= dp_bsn_align_src_out_arr; --BSN aligned streams
- dp_bsn_monitor_input_in_siso_arr(5 DOWNTO 3) <= dp_fifo_fill_src_in_arr;
+ reg_mosi => reg_dp_bsn_align_mosi_arr(i),
+ reg_miso => reg_dp_bsn_align_miso_arr(i)
+ );
+ END GENERATE;
- u_dp_bsn_monitor_input : ENTITY dp_lib.mms_dp_bsn_monitor
- GENERIC MAP (
- g_nof_streams => c_nof_10GbE_streams*2,
- g_sync_timeout => 225280000, --200000000*1.024*1.1 (1.1 = margin)
- g_log_first_bsn => FALSE
+ -- MM bus multiplexer
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => ceil_log2(c_nof_10GbE_streams)
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_dp_bsn_monitor_input_mosi,
- reg_miso => reg_dp_bsn_monitor_input_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- sync_in => dp_pps,
- in_siso_arr => dp_bsn_monitor_input_in_siso_arr,
- in_sosi_arr => dp_bsn_monitor_input_in_sosi_arr
+ mosi => reg_dp_bsn_align_mosi,
+ miso => reg_dp_bsn_align_miso,
+ mosi_arr => reg_dp_bsn_align_mosi_arr,
+ miso_arr => reg_dp_bsn_align_miso_arr
);
-------------------------------------------------------------------------------
- -- DP Sync Checker (TODO not in sim!)
- -- . Make sure there are 88 beamlets*800000 timesamples per sync pulse.
+ -- Repack the 64b 10G input data to 48b
+ -- . this is done here so we can use the pre-BSN align FIFOs (dp_sync_checker
+ -- does not support flow control).
-------------------------------------------------------------------------------
- gen_dp_sync_checker : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
- u_dp_sync_checker : ENTITY dp_lib.dp_sync_checker
- GENERIC MAP(
- g_nof_blk_per_sync => g_nof_blk_per_sync -- 800000 = 88 beamlets * 800000 timesamples / 88 (nof timesamples/block)
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- snk_out => OPEN,
- snk_in => dp_sync_checker_snk_in_arr(i),
- src_in => c_dp_siso_rdy,
- src_out => dp_sync_checker_src_out_arr(i)
- );
+ gen_dp_repack_data : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
+ gen_j : FOR j IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ u_dp_repack_data : ENTITY dp_lib.dp_repack_data
+ GENERIC MAP (
+ g_in_dat_w => 64,
+ g_in_nof_words => 3,
+ g_out_dat_w => 48,
+ g_out_nof_words => 4
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in => dp_bsn_align_src_out_2arr_3(i)(i),
+ snk_out => dp_bsn_align_src_in_2arr_3(i)(j),
+
+ src_out => dp_repack_data_src_out_2arr_3(i)(j),
+ src_in => c_dp_siso_rdy
+ );
+ END GENERATE;
END GENERATE;
+ -------------------------------------------------------------------------------
+ -- Insert a fake sync on the first frame after a reset to speed up simulation
+ -------------------------------------------------------------------------------
+ gen_nofakesync : IF g_sim = FALSE GENERATE
+ dp_sync_checker_snk_in_2arr_3 <= dp_repack_data_src_out_2arr_3;
+ END GENERATE;
+ gen_fakesync : IF g_sim = TRUE GENERATE
+ p_insert_fakesync : PROCESS(dp_sync_checker_fake_sync_enable,dp_repack_data_src_out_2arr_3)
+ BEGIN
+ FOR i IN 0 TO g_nof_cbsets-1 LOOP
+ FOR j IN 0 TO c_nof_10GbE_streams-1 LOOP
+ dp_sync_checker_snk_in_2arr_3(i)(j) <= dp_repack_data_src_out_2arr_3(i)(j); -- SOSI ctrl and data
+ dp_sync_checker_snk_in_2arr_3(i)(j).sync <= dp_repack_data_src_out_2arr_3(i)(j).sop and dp_sync_checker_fake_sync_enable; -- Override the sync
+ END LOOP;
+ END LOOP;
+ END PROCESS;
+
+ p_ctrl_fakesync : PROCESS(dp_clk,dp_rst)
+ BEGIN
+ IF dp_rst = '1' THEN
+ dp_sync_checker_fake_sync_enable <= '1';
+ ELSE
+ IF dp_clk'event and dp_clk = '1' THEN
+ FOR i IN 0 TO g_nof_cbsets-1 LOOP
+ IF dp_repack_data_src_out_2arr_3(i)(0).sop = '1' and dp_sync_checker_fake_sync_enable = '1' THEN
+ dp_sync_checker_fake_sync_enable <= '0';
+ END IF;
+ END LOOP;
+ END IF;
+ END IF;
+ END PROCESS;
+ END GENERATE;
-------------------------------------------------------------------------------
- -- DP Sync Insert (to tag beamlet boundaries)
+ -- DP Sync Checker
+ -- . Make sure there are 88 beamlets*800000 timesamples per sync pulse.
-------------------------------------------------------------------------------
- dp_sync_insert_snk_in_arr <= dp_sync_checker_src_out_arr;
-
- gen_dp_sync_insert : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
- u_dp_sync_insert : ENTITY dp_lib.dp_sync_insert
- GENERIC MAP(
- g_nof_data_per_blk => g_nof_fft_bins*g_nof_polarizations, -- 32 samples * 2 pols=64
- g_nof_blk_per_sync => g_nof_blk_per_sync/g_nof_fft_bins -- 800000/32=25000
- )
- PORT MAP(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_sync_insert_snk_in_arr(i),
-
- src_out => dp_sync_insert_src_out_arr(i)
- );
+ gen_dp_sync_checker : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
+ gen_j : FOR j IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ u_dp_sync_checker : ENTITY dp_lib.dp_sync_checker
+ GENERIC MAP(
+ g_nof_blk_per_sync => c_nof_blk_per_sync -- 800000 = 88 beamlets * 800000 timesamples / 88 (nof timesamples/block)
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ snk_in => dp_sync_checker_snk_in_2arr_3(i)(j),
+ snk_out => OPEN, -- Beware! snk_out always ready, cannot be used.
+
+ src_out => dp_sync_checker_src_out_2arr_3(i)(j),
+ src_in => c_dp_siso_rdy
+ );
+ END GENERATE;
END GENERATE;
+ -------------------------------------------------------------------------------
+ -- Concatenate 3*48b into 144b
+ -------------------------------------------------------------------------------
+ p_concatenate_3x48_to_144 : PROCESS(dp_sync_checker_src_out_2arr_3)
+ BEGIN
+ FOR i IN 0 TO g_nof_cbsets-1 LOOP
+ FOR j IN 0 TO c_nof_10GbE_streams-1 LOOP
+ concatenated_144b_sosi_arr(i) <= dp_sync_checker_src_out_2arr_3(i)(0);
+ concatenated_144b_sosi_arr(i).data(j*48+48-1 DOWNTO j*48) <= dp_sync_checker_src_out_2arr_3(i)(j).data(48-1 DOWNTO 0);
+ END LOOP;
+ END LOOP;
+ END PROCESS;
+
+ -------------------------------------------------------------------------------
+ -- Extract the 8 dish streams from the 144b data
+ -------------------------------------------------------------------------------
+ p_src_out_2arr_8:PROCESS(concatenated_144b_sosi_arr)
+ BEGIN
+ FOR i IN 0 TO g_nof_cbsets-1 LOOP
+ src_out_2arr_8(i)(7) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(7).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data(143 DOWNTO 135); --RT9
+ src_out_2arr_8(i)(7).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data(134 DOWNTO 126);
+ src_out_2arr_8(i)(6) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(6).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data(125 DOWNTO 117); --RT8
+ src_out_2arr_8(i)(6).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data(116 DOWNTO 108);
+ src_out_2arr_8(i)(5) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(5).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data(107 DOWNTO 99); --RT7
+ src_out_2arr_8(i)(5).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 98 DOWNTO 90);
+ src_out_2arr_8(i)(4) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(4).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 89 DOWNTO 81); --RT6
+ src_out_2arr_8(i)(4).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 80 DOWNTO 72);
+ src_out_2arr_8(i)(3) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(3).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 71 DOWNTO 63); --RT5
+ src_out_2arr_8(i)(3).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 62 DOWNTO 54);
+ src_out_2arr_8(i)(2) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(2).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 53 DOWNTO 45); --RT4
+ src_out_2arr_8(i)(2).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 44 DOWNTO 36);
+ src_out_2arr_8(i)(1) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(1).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 35 DOWNTO 27); --RT3
+ src_out_2arr_8(i)(1).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 26 DOWNTO 18);
+ src_out_2arr_8(i)(0) <= concatenated_144b_sosi_arr(i);
+ src_out_2arr_8(i)(0).im(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 17 DOWNTO 9); --RT2
+ src_out_2arr_8(i)(0).re(8 DOWNTO 0) <= concatenated_144b_sosi_arr(i).data( 8 DOWNTO 0);
+ END LOOP;
+ END PROCESS;
+
+ -----------------------------------------------------------------------------
+ -- Latch the bsn of the aligned streams and feed it to the output packetizer
+ -----------------------------------------------------------------------------
+ p_latch_bsn : PROCESS(dp_rst, dp_clk) IS
+ BEGIN
+ FOR i IN 0 TO g_nof_cbsets-1 LOOP
+ IF dp_rst = '1' THEN
+ general_bsn_arr(i) <= (OTHERS => '0');
+ ELSE
+ IF rising_edge(dp_clk) THEN
+ IF dp_bsn_align_src_out_2arr_3(i)(0).sync = '1' THEN
+ general_bsn_arr(i) <= dp_bsn_align_src_out_2arr_3(i)(0).bsn;
+ END IF;
+ END IF;
+ END IF;
+ END LOOP;
+ END PROCESS;
-
END str;
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_mm_master.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_mm_master.vhd
index 18888734dd..2137f21e15 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_mm_master.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_mm_master.vhd
@@ -130,7 +130,10 @@ ENTITY arts_unb2b_sc3_mm_master IS
reg_eth10g_qsfp_ring_mosi : OUT t_mem_mosi;
- reg_eth10g_qsfp_ring_miso : IN t_mem_miso
+ reg_eth10g_qsfp_ring_miso : IN t_mem_miso;
+
+ reg_dp_bsn_align_mosi : OUT t_mem_mosi;
+ reg_dp_bsn_align_miso : IN t_mem_miso
);
END arts_unb2b_sc3_mm_master;
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_output.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_output.vhd
index 19c04c5e3a..d9d46c27c4 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_output.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_output.vhd
@@ -25,15 +25,18 @@
-- Purpose:
-- . Transpose and packetize the input streams to 40 (CB) IQUV and I output streams
-- Input : src_out_2arr
--- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
--- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
--- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
--- Output: iquv_src_out_arr
+-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
+-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
+-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
+-- Output: src_out_arr
+-- . TODO
+-- Description:
+-- . The CB set outputs 0.. 7 connect to QSFP_0_TX..QSFP_1_TX.
+-- . FIXME arts_unb1_sc4_output_tab is using way too much MM address space
+-- . too many header fields are MM controllable
+-- . Why is MM control of IP, MAC duplicated?
--- Output: i_src_out_arr
-
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -43,26 +46,188 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY arts_unb2b_sc3_output IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10_e1sg;
- g_sim : BOOLEAN := FALSE;
- g_nof_cbsets : NATURAL,
- g_nof_tabs : NATURAL;
- g_iquv_data_w_out : NATURAL
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE;
+ g_nof_cbsets : NATURAL;
+ g_nof_cb_per_set : NATURAL;
+ g_nof_subbands_per_cb : NATURAL;
+ g_nof_channels : NATURAL;
+ g_nof_timesamples : NATURAL;
+ g_nof_tabs : NATURAL;
+ g_iquv_data_w_out : NATURAL
);
PORT (
- src_out_2arr : IN t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
- iquv_src_out_arr : OUT t_dp_sosi_arr(g_nof_cb-1 DOWNTO 0); -- 40 CB
- i_src_out_arr : OUT t_dp_sosi_arr(g_nof_cb-1 DOWNTO 0) -- 40 CB
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ snk_in_2arr_9 : IN t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
+ general_bsn_arr : IN t_slv_64_arr(g_nof_cbsets-1 DOWNTO 0);
+
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * I and IQUV interleaved
+ src_in_arr : IN t_dp_siso_arr(g_nof_cbsets-1 DOWNTO 0);
+
+ reg_dp_offload_tx_tab_iquv_hdr_dat_mosi : IN t_mem_mosi;
+ reg_dp_offload_tx_tab_iquv_hdr_dat_miso : OUT t_mem_miso;
+ reg_dp_xonoff_tab_iquv_mosi : IN t_mem_mosi;
+ reg_dp_xonoff_tab_iquv_miso : OUT t_mem_miso;
+ reg_dp_offload_tx_tab_i_hdr_dat_mosi : IN t_mem_mosi;
+ reg_dp_offload_tx_tab_i_hdr_dat_miso : OUT t_mem_miso;
+ reg_tab_dest_ip_mosi : IN t_mem_mosi;
+ reg_tab_dest_ip_miso : OUT t_mem_miso;
+ reg_tab_dest_mac_mosi : IN t_mem_mosi;
+ reg_tab_dest_mac_miso : OUT t_mem_miso;
+ reg_dp_xonoff_tab_i_mosi : IN t_mem_mosi;
+ reg_dp_xonoff_tab_i_miso : OUT t_mem_miso;
+
+ ID : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0)
);
END arts_unb2b_sc3_output;
ARCHITECTURE str OF arts_unb2b_sc3_output IS
+ SIGNAL reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_xonoff_tab_iquv_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_xonoff_tab_iquv_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_tab_dest_ip_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_tab_dest_ip_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_tab_dest_mac_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_tab_dest_mac_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_xonoff_tab_i_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL reg_dp_xonoff_tab_i_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
-
+ SIGNAL unb1_id : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
BEGIN
+
+ gen_arts_unb1_sc4_output_tab : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
+-- u_arts_unb1_sc4_output_tab : ENTITY arts_unb1_sc4_lib.arts_unb1_sc4_output_tab --workaround, can't include unb1 libs in unb2b QuestaSim
+ u_arts_unb1_sc4_output_tab : ENTITY work.arts_unb1_sc4_output_tab
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_override_payload_data => FALSE,
+ g_nof_tabs => g_nof_tabs,
+ g_nof_compound_beams => g_nof_cb_per_set,
+ g_nof_subbands_per_compound_beam => g_nof_subbands_per_cb,
+ g_nof_stokes => 4,
+ g_nof_channels => g_nof_channels,
+ g_nof_timesamples => g_nof_timesamples,
+ g_nof_bytes_per_iquv_packet => 8000,
+ g_nof_bytes_per_i_packet => 6250
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ general_bsn => general_bsn_arr(i),
+ tab_snk_in_arr => snk_in_2arr_9(i),
+ tab_src_out => src_out_arr(i),
+ tab_src_in => src_in_arr(i),
+
+ reg_dp_offload_tx_iquv_hdr_dat_mosi => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr(i),
+ reg_dp_offload_tx_iquv_hdr_dat_miso => reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr(i),
+ reg_dp_xonoff_iquv_mosi => reg_dp_xonoff_tab_iquv_mosi_arr(i),
+ reg_dp_xonoff_iquv_miso => reg_dp_xonoff_tab_iquv_miso_arr(i),
+ reg_dp_offload_tx_i_hdr_dat_mosi => reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr(i),
+ reg_dp_offload_tx_i_hdr_dat_miso => reg_dp_offload_tx_tab_i_hdr_dat_miso_arr(i),
+ reg_tab_dest_ip_mosi => reg_tab_dest_ip_mosi_arr(i),
+ reg_tab_dest_ip_miso => reg_tab_dest_ip_miso_arr(i),
+ reg_tab_dest_mac_mosi => reg_tab_dest_mac_mosi_arr(i),
+ reg_tab_dest_mac_miso => reg_tab_dest_mac_miso_arr(i),
+ reg_dp_xonoff_i_mosi => reg_dp_xonoff_tab_i_mosi_arr(i),
+ reg_dp_xonoff_i_miso => reg_dp_xonoff_tab_i_miso_arr(i),
+
+ ID => unb1_id
+ );
+
+ -- Convert unb2 ID + CB set index to unb1 ID
+ -- . CB set index = unb1 chip ID
+ -- . unb2 backplane index && unb2 chip ID = unb1 backplane ID (band 0..15)
+ unb1_id <= ID(4 DOWNTO 0) & TO_UVEC(i, 3);
+ END GENERATE;
+
+ -- MM bus multiplexers
+ u_common_mem_mux_reg_dp_offload_tx_tab_iquv_hdr_dat : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 6
+ )
+ PORT MAP (
+ mosi => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi,
+ miso => reg_dp_offload_tx_tab_iquv_hdr_dat_miso,
+ mosi_arr => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr,
+ miso_arr => reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr
+ );
+
+ u_common_mem_mux_reg_dp_xonoff_tab_iquv : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 1
+ )
+ PORT MAP (
+ mosi => reg_dp_xonoff_tab_iquv_mosi,
+ miso => reg_dp_xonoff_tab_iquv_miso,
+ mosi_arr => reg_dp_xonoff_tab_iquv_mosi_arr,
+ miso_arr => reg_dp_xonoff_tab_iquv_miso_arr
+ );
+
+ u_common_mem_mux_reg_dp_offload_tx_tab_i_hdr_dat : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 9
+ )
+ PORT MAP (
+ mosi => reg_dp_offload_tx_tab_i_hdr_dat_mosi,
+ miso => reg_dp_offload_tx_tab_i_hdr_dat_miso,
+ mosi_arr => reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr,
+ miso_arr => reg_dp_offload_tx_tab_i_hdr_dat_miso_arr
+ );
+
+ u_common_mem_mux_reg_tab_dest_ip : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 3
+ )
+ PORT MAP (
+ mosi => reg_tab_dest_ip_mosi,
+ miso => reg_tab_dest_ip_miso,
+ mosi_arr => reg_tab_dest_ip_mosi_arr,
+ miso_arr => reg_tab_dest_ip_miso_arr
+ );
+
+ u_common_mem_mux_reg_tab_dest_mac : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 4
+ )
+ PORT MAP (
+ mosi => reg_tab_dest_mac_mosi,
+ miso => reg_tab_dest_mac_miso,
+ mosi_arr => reg_tab_dest_mac_mosi_arr,
+ miso_arr => reg_tab_dest_mac_miso_arr
+ );
+
+ u_common_mem_mux_reg_dp_xonoff_tab_i : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => 1
+ )
+ PORT MAP (
+ mosi => reg_dp_xonoff_tab_i_mosi,
+ miso => reg_dp_xonoff_tab_i_miso,
+ mosi_arr => reg_dp_xonoff_tab_i_mosi_arr,
+ miso_arr => reg_dp_xonoff_tab_i_miso_arr
+ );
+
END str;
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_processing.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_processing.vhd
index bef97902ea..6fd0b9ef11 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_processing.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_processing.vhd
@@ -23,16 +23,16 @@
-- Authors:
-- . Daniel van der Schuur
-- Purpose: Create 9 TABs + integrated Stokes params for 40 Compound Beams
--- . Input: snk_in_2arr
+-- . Input: snk_in_2arr_8
-- . [8 CB sets * 8 dishes] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<--- 64 streams --->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 64 streams * 3.375 Gbps = 216 Gbps ---------------------------->)
--- . Output: src_out_2arr
+-- . Output: src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib, arts_tab_beamformer_lib, iquv_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -51,18 +51,46 @@ ENTITY arts_unb2b_sc3_processing IS
g_nof_beamlets : NATURAL;
g_nof_tabs : NATURAL;
g_iquv_nof_int : NATURAL;
- g_iquv_data_w_out : NATURAL;
+ g_iquv_data_w_out : NATURAL
);
PORT (
- snk_in_2arr : IN t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0), -- 8 CB sets * 8 dishes
- src_out_2arr : OUT t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0) -- 8 CB sets * 9 TABs
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ snk_in_2arr_8 : IN t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
+ src_out_2arr_9 : OUT t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
+
+ ram_arts_tab_beamformer_mosi : IN t_mem_mosi;
+ ram_arts_tab_beamformer_miso : OUT t_mem_miso := c_mem_miso_rst
);
END arts_unb2b_sc3_processing;
ARCHITECTURE str OF arts_unb2b_sc3_processing IS
+ -------------------------------------------------------------------------------
+ -- arts_tab_beamformer
+ -------------------------------------------------------------------------------
+ SIGNAL arts_tab_beamformer_src_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
+
+ SIGNAL ram_arts_tab_beamformer_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL ram_arts_tab_beamformer_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
+
+
+
+ -------------------------------------------------------------------------------
+ -- IQUV
+ -------------------------------------------------------------------------------
CONSTANT c_iquv_data_w_in : NATURAL := 2*g_data_w; --TAB BF output width --FIXME Do we really need 18b complex on 72 streams?
+ CONSTANT c_out_data_w_iquv : NATURAL := 8;
+
+ SIGNAL iquv_i_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL iquv_q_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL iquv_u_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
+ SIGNAL iquv_v_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
BEGIN
@@ -70,11 +98,11 @@ BEGIN
-- arts_tab_beamformer (8x):
-- . Purpose:
-- . Create 9 TABs per CB
- -- . Input: snk_in_2arr
+ -- . Input: snk_in_2arr_8
-- . [8 CB sets * 8 dishes] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<--- 64 streams --->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 64 streams * 3.375 Gbps = 216 Gbps ---------------------------->)
- -- . Output: arts_tab_beamformer_src_out_2arr
+ -- . Output: arts_tab_beamformer_src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 72 streams * 3.375 Gbps = 243 Gbps -------------------------->)
@@ -99,23 +127,36 @@ BEGIN
ram_mosi => ram_arts_tab_beamformer_mosi_arr(i),
ram_miso => ram_arts_tab_beamformer_miso_arr(i),
- snk_in_arr => snk_in_2arr(i),
- src_out_arr => arts_tab_beamformer_src_out_2arr(i)
+ snk_in_arr => snk_in_2arr_8(i),
+ src_out_arr => arts_tab_beamformer_src_out_2arr_9(i)
);
END GENERATE;
+ -- MM bus multiplexer
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_cbsets,
+ g_mult_addr_w => ceil_log2(2*g_nof_beamlets)
+ )
+ PORT MAP (
+ mosi => ram_arts_tab_beamformer_mosi,
+ miso => ram_arts_tab_beamformer_miso,
+ mosi_arr => ram_arts_tab_beamformer_mosi_arr,
+ miso_arr => ram_arts_tab_beamformer_miso_arr
+ );
+
-------------------------------------------------------------------------------
-- IQUV
-- . Purpose:
-- . For each TAB, calculate IQUV + integrate 1/16
- -- . Input: arts_tab_beamformer_src_out_2arr
- -- . Output: src_out_2arr
+ -- . Input: arts_tab_beamformer_src_out_2arr_9
+ -- . Output: src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
-------------------------------------------------------------------------------
- gen_arts_tab_beamformer : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
- gen_iquv : FOR j IN 0 TO g_nof_tabs-1 GENERATE
+ gen_iquv : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
+ gen_j : FOR j IN 0 TO g_nof_tabs-1 GENERATE
u_iquv : ENTITY iquv_lib.iquv
GENERIC MAP (
g_sim => g_sim,
@@ -128,19 +169,19 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
- in_complex => arts_tab_beamformer_src_out_2arr(i)(j),
+ in_complex => arts_tab_beamformer_src_out_2arr_9(i)(j),
- i_out => src_out_2arr(i)(j),
- q_out => src_out_2arr(i)(j),
- u_out => src_out_2arr(i)(j),
- v_out => src_out_2arr(i)(j)
+ i_out => iquv_i_out_2arr_9(i)(j),
+ q_out => iquv_q_out_2arr_9(i)(j),
+ u_out => iquv_u_out_2arr_9(i)(j),
+ v_out => iquv_v_out_2arr_9(i)(j)
);
- src_out_2arr(i)(j).valid <= iquv_iab_i_out.valid;
- src_out_2arr(i)(j).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
- & iquv_u_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
- & iquv_q_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
- & iquv_i_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0);
+ src_out_2arr_9(i)(j).valid <= iquv_i_out_2arr_9(i)(0).valid;
+ src_out_2arr_9(i)(j).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
+ & iquv_u_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
+ & iquv_q_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
+ & iquv_i_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0);
END GENERATE;
END GENERATE;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 2697eca675..9d2f4bbb05 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -34,6 +34,7 @@ ENTITY unb2_board_10gbe IS
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
g_technology : NATURAL := c_tech_arria10;
g_nof_macs : NATURAL;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
@@ -99,6 +100,7 @@ BEGIN
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => g_nof_macs,
+ g_direction => g_direction,
g_tx_fifo_fill => g_tx_fifo_fill,
g_tx_fifo_size => g_tx_fifo_size
)
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index be50155fb5..7b331603b5 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -12,6 +12,9 @@ hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_
ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48
+ ip_arria10_e1sg_phy_10gbase_r_3
+ ip_arria10_e1sg_transceiver_reset_controller_3
+
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -38,12 +41,14 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+ ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+ ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index cb53d02d2b..a4bfba0a13 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -22,6 +22,7 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
@@ -214,7 +215,86 @@ BEGIN
END GENERATE;
END GENERATE;
+ gen_phy_3 : IF c_nof_channels_per_ip=3 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e1sg_phy_10gbase_r_3 : ip_arria10_e1sg_phy_10gbase_r_3
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ u_ip_arria10_e1sg_transceiver_reset_controller_3 : ip_arria10_e1sg_transceiver_reset_controller_3
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
@@ -227,7 +307,7 @@ BEGIN
rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
END GENERATE;
-
+
u_ip_arria10_e1sg_phy_10gbase_r_4 : ip_arria10_e1sg_phy_10gbase_r_4
PORT MAP (
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index 498e0f9798..e53273e5bb 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -843,6 +843,61 @@ PACKAGE tech_10gbase_r_component_pkg IS
unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
END COMPONENT;
+
+ component ip_arria10_e1sg_phy_10gbase_r_3 is
+ port (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ rx_clkout : out std_logic_vector(2 downto 0); -- clk
+ rx_control : out std_logic_vector(23 downto 0); -- rx_control
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(2 downto 0); -- rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(2 downto 0); -- rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(2 downto 0); -- rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(2 downto 0); -- rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(2 downto 0); -- rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
+ rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
+ rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_serial_data
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_seriallpbken
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
+ tx_clkout : out std_logic_vector(2 downto 0); -- clk
+ tx_control : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_control
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_err_ins
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
+ unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => 'X'); -- unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X') -- unused_tx_parallel_data
+ );
+ end component ip_arria10_e1sg_phy_10gbase_r_3;
+
COMPONENT ip_arria10_e1sg_phy_10gbase_r_4
port (
@@ -1105,6 +1160,25 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
+ component ip_arria10_e1sg_transceiver_reset_controller_3 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
+ tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
+ tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ );
+ end component ip_arria10_e1sg_transceiver_reset_controller_3;
+
COMPONENT ip_arria10_e1sg_transceiver_reset_controller_4
port (
clock : in std_logic := '0'; -- clock.clk
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
new file mode 100644
index 0000000000..ee72e73fa0
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
new file mode 100755
index 0000000000..3240ee8311
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r_3.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
new file mode 100644
index 0000000000..54dc096906
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_3
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r_3.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
new file mode 100644
index 0000000000..8eebf9a668
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qsys
@@ -0,0 +1,628 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r_3">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="17.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="3" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
new file mode 100644
index 0000000000..af3b3937c3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
+
+ vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
new file mode 100755
index 0000000000..ed92ce368e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_3.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
new file mode 100644
index 0000000000..591a426a5d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_3
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_3.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
new file mode 100644
index 0000000000..fad8e19b9a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_3">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="17.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="3" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
--
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