Skip to content
Snippets Groups Projects
Commit a76dd3f3 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
Browse files

Lofar2 adc multichannel test bench now working with 3 inputs

parent ba32b086
No related branches found
No related tags found
2 merge requests!28Master,!16Resolve L2SDP-25
Expand all Hide whitespace changes
Inline Side-by-side
Showing
with 910 additions and 134 deletions
applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+ 2
− 0
View file @ a76dd3f3
......@@ -17,6 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
tb/wave/wave_multichannel.do .
tb/wave/readregs.do .
[quartus_project_file]
......
applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+ 127
− 29
View file @ a76dd3f3
......@@ -55,26 +55,26 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_bondingclk_period : TIME := 10 ns;
CONSTANT c_sysref_period : NATURAL := 20000; -- number of sample clocks between sysref pulses
CONSTANT c_sysref_period : NATURAL := 10000; -- number of sample clocks between sysref pulses
-- Transport delays
TYPE t_time_arr IS ARRAY (11 DOWNTO 0) OF TIME;
TYPE t_time_arr IS ARRAY (0 TO 11) OF TIME;
CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
CONSTANT c_delay_data_arr : t_time_arr := (800 ps,
900 ps,
950 ps,
800 ps,
900 ps,
950 ps,
800 ps,
900 ps,
950 ps,
800 ps,
900 ps,
950 ps) ; -- transport delays tx to rx data
CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (1000 ps,
1000 ps,
1000 ps,
CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps,
5000 ps) ; -- transport delays tx to rx data
CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
5000 ps,
6000 ps,
1000 ps,
1000 ps,
1000 ps,
......@@ -84,7 +84,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
1000 ps,
1000 ps,
1000 ps) ; -- transport delays clock source to adc(tx)
CONSTANT c_delay_sysreftofpga : TIME := 1000 ps;
CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
......@@ -154,6 +154,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
-- Diagnostic signals
SIGNAL avs_chipselect : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL avs_read : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL avs_readdata : t_slv_32_arr(11 DOWNTO 0);
SIGNAL avs_address : t_slv_8_arr(11 DOWNTO 0);
BEGIN
......@@ -232,10 +238,10 @@ BEGIN
-----------------------------------------------------------------------------
gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
-- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
jesd204b_sync_adc(i) <= transport jesd204b_sync_fpga(i) after c_delay_data_arr(i);
END GENERATE;
......@@ -267,10 +273,10 @@ BEGIN
csr_tx_testpattern_d => OPEN,
csr_s => OPEN,
dev_sync_n => dev_sync_n(i), --out
jesd204_tx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
jesd204_tx_avs_address => (others => '0'),
jesd204_tx_avs_read => '0',
jesd204_tx_avs_readdata => open,
jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
jesd204_tx_avs_address => avs_address(i),
jesd204_tx_avs_read => avs_read(i),
jesd204_tx_avs_readdata => avs_readdata(i),
jesd204_tx_avs_waitrequest => open,
jesd204_tx_avs_write => '0',
jesd204_tx_avs_writedata => (others => '0'),
......@@ -303,29 +309,47 @@ BEGIN
proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
VARIABLE data : INTEGER := 0;
VARIABLE even_sample : BOOLEAN := TRUE;
BEGIN
IF mm_rst = '1' THEN
jesd204b_tx_link_data_arr(i) <= (others => '0');
jesd204b_tx_link_valid(i) <= '0';
txlink_clk(i) <= '0';
data := 0;
even_sample := TRUE;
ELSE
IF rising_edge(jesd204b_sampclk_adc(i)) THEN
jesd204b_tx_link_valid(i) <= '1';
txlink_clk(i) <= not txlink_clk(i);
jesd204b_tx_link_data_arr(i) <= TO_SVEC(data, 32);
jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
IF (jesd204b_sysref_adc_1(i) = '1') THEN
IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
data := 1000;
ELSIF (jesd204b_sysref_adc_2(i) = '1') THEN
ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
data := -1000;
ELSE
data := 0;
END IF;
-- Frame the data to 32 bits at half the rate
IF(jesd204b_tx_link_ready(i) = '0') THEN
even_sample := TRUE;
ELSE
even_sample := not even_sample;
END IF;
IF (even_sample = TRUE) THEN
jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
jesd204b_tx_link_valid(i) <= '0';
ELSE
jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
jesd204b_tx_link_valid(i) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
......@@ -382,7 +406,7 @@ BEGIN
count := count + 1;
END IF;
IF count > c_sysref_period-40 THEN
IF count > c_sysref_period-8 THEN
jesd204b_sysref <= '1';
ELSE
jesd204b_sysref <= '0';
......@@ -390,8 +414,82 @@ BEGIN
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
-- Diagnostics
------------------------------------------------------------------------------
proc_read_avs_regs : PROCESS
BEGIN
wait for 100ns;
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait until avs_rst_n = '1';
while true loop
wait until rising_edge(mm_clk);
avs_address(0) <= X"14"; -- dll control
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
avs_address(0) <= X"15"; -- syncn_sysref control
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
avs_address(0) <= X"18"; -- syncn_sysref control
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
avs_address(0) <= X"19"; -- syncn_sysref control
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
avs_address(0) <= X"20"; -- tx control0
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
wait until rising_edge(mm_clk);
avs_address(0) <= X"26"; -- tx control0
avs_chipselect(0) <= '1';
avs_read(0) <= '1';
wait for c_mm_clk_period * 1;
wait until rising_edge(mm_clk);
avs_address(0) <= (others => '0');
avs_chipselect(0) <= '0';
avs_read(0) <= '0';
wait for c_mm_clk_period * 32;
END LOOP;
END PROCESS;
------------------------------------------------------------------------------
-- Simulation end
......
applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/readregs.do 0 → 100644
+ 61
− 0
View file @ a76dd3f3
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_read 1 0
force -drive sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_chipselect 1 0
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h14 0
run 200ns
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h15 0
run 200ns
# 0x60 rx_err0
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h18 0
run 200ns
# 0x64 rx_err1
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h19 0
run 200ns
# 0x80 rx_status0
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h20 0
run 200ns
# 0x84 rx_status1
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h21 0
run 200ns
# 0x88 rx_status2
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h22 0
run 200ns
# 0x8C rx_status2
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h23 0
run 200ns
# 0x94 ilas_data1
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h25 0
run 200ns
# 0x98 ilas_data2
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h26 0
run 200ns
# 0xF0 rx_status4
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3C 0
run 200ns
# 0xF4 rx_status5
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3D 0
run 200ns
# 0xF8 rx_status6
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3E 0
run 200ns
# 0xFC rx_status7
force -freeze sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address 8'h3F 0
run 200ns
noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_chipselect
noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_address
noforce sim:/tb_lofar2_unb2b_adc_multichannel/u_lofar_unb2b_adc/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_channels(0)/u_ip_arria10_e1sg_jesd204b_rx/jesd204_0/jesd204_rx_avs_read
applications/lofar2/designs/lofar2_unb2b_adc/tb/wave/wave_multichannel.do 0 → 100644
+ 680
− 0
View file @ a76dd3f3
This diff is collapsed.
libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+ 40
− 105
View file @ a76dd3f3
......@@ -78,6 +78,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
-- Clocks
SIGNAL rxframe_clk : STD_LOGIC;
SIGNAL rxlink_clk : STD_LOGIC;
SIGNAL jesd204b_avs_clk : STD_LOGIC;
-- Reset and control signals
SIGNAL dev_lane_aligned : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, each interface channel has 1 lane
......@@ -100,64 +101,17 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL core_pll_locked : STD_LOGIC;
SIGNAL core_pll_locked_reg : STD_LOGIC;
SIGNAL jesd204b_sysref_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
-- Data path
SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(32*g_nof_channels-1 DOWNTO 0);
SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(4*g_nof_channels-1 DOWNTO 0);
-- Component declarations for the IP blocks
-- component ip_arria10_e1sg_jesd204b_rx is
-- port (
-- jesd204_0_alldev_lane_aligned_export : in std_logic := 'X'; -- export
-- csr_cf_export : out std_logic_vector(4 downto 0); -- export
-- csr_cs_export : out std_logic_vector(1 downto 0); -- export
-- csr_f_export : out std_logic_vector(7 downto 0); -- export
-- csr_hd_export : out std_logic; -- export
-- csr_k_export : out std_logic_vector(4 downto 0); -- export
-- csr_l_export : out std_logic_vector(4 downto 0); -- export
-- csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
-- csr_m_export : out std_logic_vector(7 downto 0); -- export
-- csr_n_export : out std_logic_vector(4 downto 0); -- export
-- csr_np_export : out std_logic_vector(4 downto 0); -- export
-- csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
-- csr_s_export : out std_logic_vector(4 downto 0); -- export
-- dev_lane_aligned_export : out std_logic; -- export
-- dev_sync_n_export : out std_logic; -- export
-- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
-- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
-- jesd204_rx_avs_read : in std_logic := 'X'; -- read
-- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
-- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
-- jesd204_rx_avs_write : in std_logic := 'X'; -- write
-- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
-- jesd204_rx_avs_clk_clk : in std_logic := 'X'; -- clk
-- jesd204_rx_avs_rst_n_reset_n : in std_logic := 'X'; -- reset_n
-- jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
-- jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
-- jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
-- jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
-- jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
-- jesd204_rx_int_irq : out std_logic; -- irq
-- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
-- jesd204_rx_link_valid : out std_logic; -- valid
-- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
-- pll_ref_clk_clk : in std_logic := 'X'; -- clk
-- rx_analogreset_rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
-- rx_cal_busy_rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
-- rx_digitalreset_rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
-- rx_islockedtodata_rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
-- rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
-- rxlink_clk_clk : in std_logic := 'X'; -- clk
-- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
-- rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
-- sof_export : out std_logic_vector(3 downto 0); -- export
-- somf_export : out std_logic_vector(3 downto 0); -- export
-- sysref_export : in std_logic := 'X' -- export
-- );
-- end component ip_arria10_e1sg_jesd204b_rx;
component ip_arria10_e1sg_jesd204b_rx is
port (
......@@ -262,6 +216,15 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
BEGIN
jesd204b_frame_clk <= rxframe_clk;
gen_simclock : IF g_sim = TRUE GENERATE
jesd204b_avs_clk <= rxlink_clk;
END GENERATE;
gen_synthclock : IF g_sim = FALSE GENERATE
jesd204b_avs_clk <= mm_clk;
END GENERATE;
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
......@@ -269,56 +232,6 @@ BEGIN
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
-- u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx
-- PORT MAP
-- (
-- jesd204_0_alldev_lane_aligned_export => dev_lane_aligned_arr(i),
-- csr_cf_export => OPEN,
-- csr_cs_export => OPEN,
-- csr_f_export => OPEN,
-- csr_hd_export => OPEN,
-- csr_k_export => OPEN,
-- csr_l_export => OPEN,
-- csr_lane_powerdown_export => rx_csr_lane_powerdown_arr(i downto i),
-- csr_m_export => OPEN,
-- csr_n_export => OPEN,
-- csr_np_export => OPEN,
-- csr_rx_testmode_export => OPEN,
-- csr_s_export => OPEN,
-- dev_lane_aligned_export => dev_lane_aligned_arr(i),
-- dev_sync_n_export => jesd204b_sync_n_arr(i),
-- jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
-- jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0),
-- jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
-- jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0),
-- jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
-- jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
-- jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
-- jesd204_rx_avs_clk_clk => mm_clk,
-- jesd204_rx_avs_rst_n_reset_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
-- jesd204_rx_dlb_data_export => (others => '0'), -- debug/loopback testing
-- jesd204_rx_dlb_data_valid_export => (others => '0'), -- debug/loopback testing
-- jesd204_rx_dlb_disperr_export => (others => '0'), -- debug/loopback testing
-- jesd204_rx_dlb_errdetect_export => (others => '0'), -- debug/loopback testing
-- jesd204_rx_dlb_kchar_data_export => (others => '0'), -- debug/loopback testing
-- jesd204_rx_frame_error_export => '0', -- jesd204_rx_frame_error.export
-- jesd204_rx_int_irq => OPEN, -- Connected to status IO in example design
-- jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
-- jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
-- jesd204_rx_link_ready => '1',
-- pll_ref_clk_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
-- rx_analogreset_rx_analogreset => rx_analogreset_arr(I DOWNTO I),
-- rx_cal_busy_rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
-- rx_digitalreset_rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
-- rx_islockedtodata_rx_is_lockedtodata => rx_islockedtodata_arr(I DOWNTO I),
-- rx_serial_data_rx_serial_data => serial_rx_arr(i downto i),
-- rxlink_clk_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
-- rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
-- rxphy_clk_export => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
-- sof_export => OPEN,
-- somf_export => OPEN,
-- sysref_export => jesd204b_sysref
-- );
u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx
PORT MAP
......@@ -345,7 +258,7 @@ BEGIN
jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
jesd204_rx_avs_clk => mm_clk,
jesd204_rx_avs_clk => jesd204b_avs_clk, --mm_clk,
jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing
jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing
......@@ -367,8 +280,8 @@ BEGIN
rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
sof => OPEN,
somf => OPEN,
sysref => jesd204b_sysref
somf => jesd204b_rx_somf_arr(4*i+3 downto 4*i),
sysref => jesd204b_sysref_2
);
-----------------------------------------------------------------------------
......@@ -407,6 +320,7 @@ BEGIN
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
......@@ -415,16 +329,20 @@ BEGIN
IF rising_edge(rxframe_clk) THEN
IF rxframe_rst_n_arr(i) = '0' THEN
rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
rx_src_out_arr(i).channel(1 downto 0) <= (OTHERS => '0');
f2_div1_cnt_arr(i) <= '0';
ELSE
rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
IF jesd204b_rx_link_valid_arr(i) = '0' THEN
rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
rx_src_out_arr(i).channel(1 downto 0) <= (OTHERS => '0');
ELSE
IF f2_div1_cnt_arr(i) = '1' THEN
rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i);
rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i);
rx_src_out_arr(i).channel(1 downto 0) <= jesd204b_rx_somf_arr(4*i+1 downto 4*i);
ELSE
rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
rx_src_out_arr(i).channel(1 downto 0) <= jesd204b_rx_somf_arr(4*i+3 downto 4*i+2);
END IF;
f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
END IF;
......@@ -433,6 +351,23 @@ BEGIN
END PROCESS;
END GENERATE;
-----------------------------------------------------------------------------
-- Reclock sysref
-----------------------------------------------------------------------------
p_reclocksysref : PROCESS (rxlink_clk, core_pll_locked)
BEGIN
IF core_pll_locked = '0' THEN
jesd204b_sysref_1 <= '0';
jesd204b_sysref_2 <= '0';
ELSE
IF rising_edge(rxlink_clk) THEN
jesd204b_sysref_1 <= jesd204b_sysref;
jesd204b_sysref_2 <= jesd204b_sysref_1;
END IF;
END IF;
END PROCESS;
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment