Use hdl_lib_include_ip to identify the DDR IP instead of via hdl_lib_excludes.

9879fb9a · Eric Kooistra · b33aa850 · 9879fb9a · 9879fb9a · 9879fb9a
Commit 9879fb9a authored 8 years ago by Eric Kooistra
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_10GbE_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
-                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000
-                   ip_arria10_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
                   ip_arria10_transceiver_reset_controller_1

 synth_files =

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_1GbE_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
-                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000
-                   ip_arria10_mac_10g
+hdl_lib_excludes = ip_arria10_mac_10g

 synth_files =
    unb2_test_1GbE.vhd

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2_test_all_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000
-                   ip_arria10_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
                   ip_arria10_transceiver_reset_controller_1

 synth_files =

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
-                   ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
                   ip_arria10_mac_10g
                   ip_arria10_phy_10gbase_r
                   ip_arria10_phy_10gbase_r_24
                   ip_arria10_transceiver_pll_10g
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
-                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000

 synth_files =
    unb2_test_ddr_MB_I.vhd

--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,15 @@ hdl_library_clause_name = unb2_test_ddr_MB_II_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
-                   ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
                   ip_arria10_mac_10g
                   ip_arria10_phy_10gbase_r
                   ip_arria10_phy_10gbase_r_24
                   ip_arria10_transceiver_pll_10g
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
-                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000
-
+                   
 synth_files =
    unb2_test_ddr_MB_II.vhd


--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
-                   ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
                   ip_arria10_mac_10g
                   ip_arria10_phy_10gbase_r
                   ip_arria10_phy_10gbase_r_24
                   ip_arria10_transceiver_pll_10g
                   ip_arria10_transceiver_reset_controller_1
                   ip_arria10_transceiver_reset_controller_24
-                   ip_arria10_ddr4_8g_2400
-                   ip_arria10_ddr4_4g_2000

 synth_files =
    unb2_test_ddr_MB_I_II.vhd

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -3,11 +3,7 @@ hdl_library_clause_name = unb2a_test_10GbE_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_ddr4_8g_1600
-                   ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
                   ip_arria10_e3sge3_transceiver_reset_controller_1

 synth_files =

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2a_test_1GbE_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
-                   ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_mac_10g
+hdl_lib_excludes = ip_arria10_e3sge3_mac_10g

 synth_files =
    unb2a_test_1GbE.vhd

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2a_test_all_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
                   ip_arria10_e3sge3_transceiver_reset_controller_1
                   
 synth_files =

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
-                   ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
                   ip_arria10_e3sge3_mac_10g
                   ip_arria10_e3sge3_phy_10gbase_r
                   ip_arria10_e3sge3_phy_10gbase_r_24
                   ip_arria10_e3sge3_transceiver_pll_10g
                   ip_arria10_e3sge3_transceiver_reset_controller_1
                   ip_arria10_e3sge3_transceiver_reset_controller_24
-                   ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_ddr4_4g_1600

 synth_files =
    unb2a_test_ddr_MB_I.vhd

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_II_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
-                   ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
                   ip_arria10_e3sge3_mac_10g
                   ip_arria10_e3sge3_phy_10gbase_r
                   ip_arria10_e3sge3_phy_10gbase_r_24
                   ip_arria10_e3sge3_transceiver_pll_10g
                   ip_arria10_e3sge3_transceiver_reset_controller_1
                   ip_arria10_e3sge3_transceiver_reset_controller_24
-                   ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_ddr4_4g_1600

 synth_files =
    unb2a_test_ddr_MB_II.vhd

--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_II_lib
 hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
-                   ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
                   ip_arria10_e3sge3_mac_10g
                   ip_arria10_e3sge3_phy_10gbase_r
                   ip_arria10_e3sge3_phy_10gbase_r_24
                   ip_arria10_e3sge3_transceiver_pll_10g
                   ip_arria10_e3sge3_transceiver_reset_controller_1
                   ip_arria10_e3sge3_transceiver_reset_controller_24
-                   ip_arria10_e3sge3_ddr4_8g_2400
-                   ip_arria10_e3sge3_ddr4_4g_2000
-                   ip_arria10_e3sge3_ddr4_4g_1600

 synth_files =
    unb2a_test_ddr_MB_I_II.vhd