diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index adbdf99c917fb0d2e5417f16b63661f1ffd76dad..2329cedf40ed58379879c6dd660567275d09213d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
ip_arria10_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 2479dbcda31bee34431be7bd172edb478672be91..398be59ba97d41445935ad02691273cb96ff57f2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_mac_10g
+hdl_lib_excludes = ip_arria10_mac_10g
synth_files =
unb2_test_1GbE.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 65eca953849b7b45dff9fdcb03652cf38f10819d..9b572e8ce7e9f1a18599fc7009690f41fa4ae376 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2_test_all_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
ip_arria10_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index e16917e8fc4450540ea88d996a51a2bd035e2b27..285fd91142854154c52a78e7c1e76ad68f24b408 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
synth_files =
unb2_test_ddr_MB_I.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index fd8757b6464767b2257e4ba16364140f098d379e..4c2a56ecc63e776f87d05e733a0a24c2ddb73943 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,15 @@ hdl_library_clause_name = unb2_test_ddr_MB_II_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
-
+
synth_files =
unb2_test_ddr_MB_II.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index f3a98983f91dc1d79e892d1022380ef564823ea1..d1be78c42d925ea4904f9c7f6f6167ad0829b219 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
synth_files =
unb2_test_ddr_MB_I_II.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 2dc9b1464a36d1fdca0d647ccfd607cb18a22a45..3e0e0dc330164d509dc122acec3410e6c324425f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -3,11 +3,7 @@ hdl_library_clause_name = unb2a_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_8g_1600
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index b01a7885c3dfc5c9b3c1969c4a48f5202f43d260..601142dbb1ba1fdfe922a86ba8b8910735de5a1f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2a_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_mac_10g
+hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
synth_files =
unb2a_test_1GbE.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 59aacc877c9f2262f9b8397ae5e99983daa299d6..1b454ab1971995f974a1b2f81b2a02099d80596e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2a_test_all_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index ef6693b1732734da279eb7aee98f8ed6454559ed..b444c71f716fcff0bb3160e7126e5a978f25bf2f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_I.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 847a9e97223913155468fe4e07093642f8a76da6..c0e9525a790021b41ef2cce7c05294c38c83b67f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_II_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_II.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 985265b3e9c65defd39da2d205784042ce36769c..a220f91241863831262a30c33ff49f3a1b56c542 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_I_II.vhd