From 9879fb9af907e10ca033026cef32f9a7c84c78f7 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 28 Apr 2016 13:28:06 +0000
Subject: [PATCH] Use hdl_lib_include_ip to identify the DDR IP instead of via
hdl_lib_excludes.
---
.../unb2_test/revisions/unb2_test_10GbE/hdllib.cfg | 5 +----
.../designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg | 5 +----
.../designs/unb2_test/revisions/unb2_test_all/hdllib.cfg | 5 ++---
.../unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg | 6 ++----
.../unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg | 8 +++-----
.../unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg | 6 ++----
.../unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg | 6 +-----
.../unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg | 5 +----
.../unb2a_test/revisions/unb2a_test_all/hdllib.cfg | 5 ++---
.../unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg | 7 ++-----
.../unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg | 7 ++-----
.../revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg | 7 ++-----
12 files changed, 21 insertions(+), 51 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index adbdf99c91..2329cedf40 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
ip_arria10_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 2479dbcda3..398be59ba9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_mac_10g
+hdl_lib_excludes = ip_arria10_mac_10g
synth_files =
unb2_test_1GbE.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 65eca95384..9b572e8ce7 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2_test_all_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
- ip_arria10_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_phy_10gbase_r
ip_arria10_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index e16917e8fc..285fd91142 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
synth_files =
unb2_test_ddr_MB_I.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index fd8757b646..4c2a56ecc6 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,15 @@ hdl_library_clause_name = unb2_test_ddr_MB_II_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
-
+
synth_files =
unb2_test_ddr_MB_II.vhd
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index f3a98983f9..d1be78c42d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -3,16 +3,14 @@ hdl_library_clause_name = unb2_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-hdl_lib_excludes = ip_arria10_tse_sgmii_gx
- ip_arria10_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_ddr4_4g_1600
+hdl_lib_excludes = ip_arria10_pll_xgmii_mac_clocks
ip_arria10_mac_10g
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_4g_2000
synth_files =
unb2_test_ddr_MB_I_II.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 2dc9b1464a..3e0e0dc330 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -3,11 +3,7 @@ hdl_library_clause_name = unb2a_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_8g_1600
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index b01a7885c3..601142dbb1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -3,10 +3,7 @@ hdl_library_clause_name = unb2a_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_mac_10g
+hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
synth_files =
unb2a_test_1GbE.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 59aacc877c..1b454ab197 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -3,9 +3,8 @@ hdl_library_clause_name = unb2a_test_all_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_phy_10gbase_r
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_transceiver_reset_controller_1
synth_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index ef6693b173..b444c71f71 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_I.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 847a9e9722..c0e9525a79 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_II_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_II.vhd
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 985265b3e9..a220f91241 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -3,17 +3,14 @@ hdl_library_clause_name = unb2a_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
-hdl_lib_excludes = ip_arria10_e3sge3_tse_sgmii_gx
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_include_ip = ip_arria10_e3sge3_ddr4_8g_1600
+hdl_lib_excludes = ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_phy_10gbase_r_24
ip_arria10_e3sge3_transceiver_pll_10g
ip_arria10_e3sge3_transceiver_reset_controller_1
ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_ddr4_8g_2400
- ip_arria10_e3sge3_ddr4_4g_2000
- ip_arria10_e3sge3_ddr4_4g_1600
synth_files =
unb2a_test_ddr_MB_I_II.vhd
--
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