post compilation temp and voltage sensors

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd

@@ -41,11 +41,11 @@ ENTITY tech_fpga_voltage_sens IS
     controller_csr_write         : in  STD_LOGIC := '0';
     controller_csr_writedata     : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
     controller_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-    sample_store_csr_address     : in  STD_LOGIC := '0';
+    sample_store_csr_address     : in  STD_LOGIC_VECTOR(3 downto 0) := "0000";
     sample_store_csr_read        : in  STD_LOGIC := '0';
     sample_store_csr_write       : in  STD_LOGIC := '0';
     sample_store_csr_writedata   : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-    controller_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+    sample_store_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
     sample_store_irq_irq         : out STD_LOGIC
   );
 END tech_fpga_voltage_sens;

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd

@@ -35,11 +35,11 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
   		controller_csr_write         : in  STD_LOGIC := '0';           
   		controller_csr_writedata     : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
   		controller_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
-  		sample_store_csr_address     : in  STD_LOGIC := '0';           
+  		sample_store_csr_address     : in  STD_LOGIC_VECTOR(3 downto 0) := "0000";           
   		sample_store_csr_read        : in  STD_LOGIC := '0';           
   		sample_store_csr_write       : in  STD_LOGIC := '0';           
   		sample_store_csr_writedata   : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
-  		controller_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
+  		sample_store_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
   		sample_store_irq_irq         : out STD_LOGIC
   	);
   END COMPONENT;

libraries/technology/technology_select_pkg.vhd

@@ -30,7 +30,7 @@ USE work.technology_pkg.ALL;
 
 PACKAGE technology_select_pkg IS
 
-  CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
-  --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+  --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+  CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
   
 END technology_select_pkg;