From 9566758511232b97b38dba8355d1ccbf3d01e4d0 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Tue, 13 Oct 2015 13:24:19 +0000
Subject: [PATCH] post compilation temp and voltage sensors
---
.../technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd | 4 ++--
.../tech_fpga_voltage_sens_component_pkg.vhd | 4 ++--
libraries/technology/technology_select_pkg.vhd | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index 2daf3a8a83..cf2c4e8d16 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -41,11 +41,11 @@ ENTITY tech_fpga_voltage_sens IS
controller_csr_write : in STD_LOGIC := '0';
controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
- sample_store_csr_address : in STD_LOGIC := '0';
+ sample_store_csr_address : in STD_LOGIC_VECTOR(3 downto 0) := "0000";
sample_store_csr_read : in STD_LOGIC := '0';
sample_store_csr_write : in STD_LOGIC := '0';
sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
- controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
sample_store_irq_irq : out STD_LOGIC
);
END tech_fpga_voltage_sens;
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 8e7206212c..87a657044a 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -35,11 +35,11 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
controller_csr_write : in STD_LOGIC := '0';
controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
- sample_store_csr_address : in STD_LOGIC := '0';
+ sample_store_csr_address : in STD_LOGIC_VECTOR(3 downto 0) := "0000";
sample_store_csr_read : in STD_LOGIC := '0';
sample_store_csr_write : in STD_LOGIC := '0';
sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
- controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
sample_store_irq_irq : out STD_LOGIC
);
END COMPONENT;
diff --git a/libraries/technology/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
index d523ac4fb9..9b94b6981a 100644
--- a/libraries/technology/technology_select_pkg.vhd
+++ b/libraries/technology/technology_select_pkg.vhd
@@ -30,7 +30,7 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
- CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
END technology_select_pkg;
--
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